Memory & FIFOs

Count-Based Sync FIFO with Dual Ready/Valid

Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.

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About this block

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Count-Based Sync FIFO with Dual Ready/Valid is a SystemVerilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

Single-clock FIFO that tracks occupancy with an explicit count register instead of comparing wide pointers. Both the producer and consumer expose ready/valid handshake signals (wready/wfull, rvalid/rempty), which makes the block easy to stitch into streaming or AXI-style interfaces.

Default configuration is 16-bit data and depth 64 (parameter DEPTH). Verified with Verilator.

Use this IP when you need a deeper buffer with explicit ready/valid on both sides and a straightforward occupancy counter. The 16-bit width is the default datapath size, not the distinguishing feature.

Choose Open in IDE. RTL Studio loads the packaged workspace for Count-Based Sync FIFO with Dual Ready/Valid.
Read the SystemVerilog module in the editor. The catalog line for this block: Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Name	Direction	Type	Description
`clk`	input	logic	Global clock (positive edge)
`rst_n`	input	logic	Active-low asynchronous reset
`wreq`	input	logic	Write request (producer)
`wdata`	input	logic [15:0]	Write data (16-bit)
`wfull`	output	logic	FIFO full (producer stall signal)
`wready`	output	logic	Write ready (=`!wfull`)
`rreq`	input	logic	Read request (consumer)
`rdata`	output	logic [15:0]	Read data (16-bit, combinational)
`rempty`	output	logic	FIFO empty (consumer stall signal)
`rvalid`	output	logic	Read valid (=`!rempty`)

Verification

Test Case	Description	Status
TC1	Reset state (empty, not full)	✅ PASS
TC2	Single write-read cycle	✅ PASS
TC3	FIFO full after burst write	✅ PASS
TC4	Rejected write on full FIFO	✅ PASS
TC5	FIFO empty after burst read	✅ PASS
TC6	Rejected read on empty FIFO	✅ PASS
TC7	Backpressure handling (write→read→write)	✅ PASS
TC8	Alternating pipeline (pipeline throughput test)	✅ PASS

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