Memory & FIFOs

32-Bit Asynchronous FIFO with Gray Pointer Encoding

A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.

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32-Bit Asynchronous FIFO with Gray Pointer Encoding is a SystemVerilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This OpenIP provides a Gray-code pointer asynchronous FIFO with AXI4-Stream style handshaking on source and destination clock domains.

The memory array is written in s_clk and read in m_clk, with synchronized pointers preventing metastable full/empty decisions.

The default configuration targets 32-bit tdata with standard tvalid/tready flow control.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Asynchronous FIFO with Gray Pointer Encoding.
Read the SystemVerilog module in the editor. The catalog line for this block: A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
`s_clk`	input	1	Source write clock
`s_rst`	input	1	Source reset (active high)
`s_axis_tdata`	input	DATA_WIDTH	Write data
`s_axis_tvalid`	input	1	Write data valid
`s_axis_tready`	output	1	Write ready
`m_clk`	input	1	Destination read clock
`m_rst`	input	1	Destination reset (active high)
`m_axis_tdata`	output	DATA_WIDTH	Read data
`m_axis_tvalid`	output	1	Read data valid
`m_axis_tready`	input	1	Read ready

Verification

Test Case	Description	Expected Behavior
TC1	Basic write/read	Sequential data 0..3 matches on read side

Run make sim from the variant directory.

Integration

Hold both resets until their respective clocks are stable, then release s_rst and m_rst in domain order required by your SoC. Size the FIFO depth parameter to cover worst-case producer/consumer rate mismatch. Tie unused AXI sideband inputs to constants when optional tkeep/tid/tdest are disabled.

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