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Memory & FIFOs

CAM 4x8 with Invalidate

A 4-entry, 8-bit Content-Addressable Memory with individual entry invalidate capability.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

CAM 4x8 with Invalidate is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 4-entry, 8-bit Content-Addressable Memory (CAM). It supports individual entry invalidation via a dedicated control interface, allowing entries to be logically disabled without erasing their stored data. This feature is useful for dynamic cache management or tag files where entries need to be retired without data loss.

### Key Features

  • Write: Updates data and marks entries as valid.
  • Invalidate: Marks specific entries as invalid without changing stored data.
  • Search: Returns the address of the first matching valid entry.
  • Synchronous Control: All control signals are synchronized to the clock edge.
  • Combinational Search: Search logic provides immediate results upon assertion of search_en.

This IP provides a simple, synchronous CAM with 4 entries and 8-bit width, featuring individual entry invalidation. It is suitable for small lookup tables, tag files, or simple associative caches where low latency and simple control are required. The search logic is combinational, providing immediate results upon assertion of search_en.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for CAM 4x8 with Invalidate.
  2. Read the Verilog module in the editor. The catalog line for this block: A 4-entry, 8-bit Content-Addressable Memory with individual entry invalidate capability.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of:

  1. A 4x8 bit storage array (cam_mem).
  2. A 4-bit validity register (valid) tracking entry status.
  3. Write Logic: Synchronous update of data and validity bit on wr_en.
  4. Invalidate Logic: Synchronous clearing of validity bit on inv_en.
  5. Search Logic: Combinational logic checking all valid entries against search_data.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low reset
wr_addrInput2Write address [1:0]
wr_dataInput8Write data [7:0]
wr_enInput1Write enable
inv_addrInput2Invalidate address [1:0]
inv_enInput1Invalidate enable
search_dataInput8Search data [7:0]
search_enInput1Search enable
match_addrOutput2Match address [1:0]
match_validOutput1Match valid flag

Verification

The provided testbench (tb_cam_invalidate_4x8.v) verifies the following scenarios:

  1. Reset: Verifies all entries are invalid after reset.
  2. Write: Writes four distinct values to all entries.
  3. Search: Verifies correct address match for each written value.
  4. No Match: Verifies no match for a non-existent value (e.g., 0xFF).
  5. Invalidate: Invalidates one entry and verifies it no longer matches.
  6. Persistence: Verifies other entries still match after invalidation.
  7. Re-write: Writes a new value to the invalidated entry and verifies it matches.

Run the simulation in RtlStudio. The Log panel should display INFO: PASS upon completion.

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