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Memory & FIFOs

32x16 Synchronous Single-Port RAM

32-word by 16-bit synchronous single-port RAM with combinational read.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

32x16 Synchronous Single-Port RAM is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 32-word by 16-bit synchronous single-port RAM. It supports synchronous writes on the positive clock edge and combinational reads, allowing data to be available immediately at the output ports based on the current address.

This IP provides a lightweight, fully verified synchronous RAM block suitable for simple data buffering, FIFO implementations, or temporary storage in FPGA designs. It features a simple interface with no reset signal, relying on power-on initialization or external reset logic if deterministic start-up is required.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 32x16 Synchronous Single-Port RAM.
  2. Read the Verilog module in the editor. The catalog line for this block: 32-word by 16-bit synchronous single-port RAM with combinational read.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The memory array consists of 32 registers, each 16 bits wide.

  • Write Operation: Controlled by the we (Write Enable) signal. Data is latched into the memory array on the positive edge of the clk signal when we is high.
  • Read Operation: Combinational. The output dout reflects the content of the memory location specified by addr immediately, without waiting for a clock edge.

This structure ensures low-latency read access while maintaining synchronous write timing.

Ports

PortDirectionWidthDescription
clkInput1Clock signal
weInput1Write enable (active high)
addrInput5Memory address (0-31)
dinInput16Write data input
doutOutput16Read data output

Integration

To integrate this IP into your design:

  1. Instantiate the module sync_ram_32x16.
  2. Connect your system clock to clk.
  3. Drive we high when you wish to write data to the address specified by addr.
  4. Read data from dout at any time; it will reflect the last written value for the current addr.

Note: Since reads are combinational, ensure that addr is stable before reading dout to avoid glitches if addr changes rapidly.

Verification

The included testbench (tb_sync_ram_32x16.v) verifies the following behaviors:

  • Combinational Read: Verifies that dout updates immediately after din and addr change, even before the clock edge.
  • Synchronous Write: Confirms data is stored only on the positive clock edge when we is asserted.
  • Data Retention: Checks that written data persists until overwritten.
  • Boundary Conditions: Tests access to the last address (index 31).
  • Burst Operations: Validates sequential write and read operations.

### Expected Simulation Results

Upon running the simulation, the log should display:

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