Memory & FIFOs

8-Bit Valid/Ready Skid Buffer

An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.

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8-Bit Valid/Ready Skid Buffer is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This repository contains a verified, depth-1 8-bit Valid/Ready skid buffer IP core designed for synchronous pipeline handshaking.

It absorbs backpressure from downstream consumers by buffering one word of data, ensuring no data loss during temporary stalls.

The implementation is lightweight, fully synchronous, and includes a comprehensive testbench for verification.

Depth-1 Buffering: Stores exactly one word of data during backpressure events.
Skid Behavior: Maintains valid_out high until valid_in deasserts, preventing data loss.
Synchronous Interface: Operates on a single clock edge (clk) with active-low reset (rst_n).
8-Bit Data Path: Supports 8-bit wide data transfers.
Fully Verified: Includes a testbench covering pass-through, backpressure, and skid consumption scenarios.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Valid/Ready Skid Buffer.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`valid_in`	Input	1	Input valid signal
`data_in`	Input	8	Input data bus
`ready_in`	Output	1	Ready to accept new data
`valid_out`	Output	1	Output valid signal
`data_out`	Output	8	Output data bus

Architecture

The module uses a single register pair to store the buffered data (buffer_data) and the valid flag (buffer_valid).

Combinational Outputs: ready_in, valid_out, and data_out are driven directly by the internal state registers.
Sequential Logic: The internal state updates on the positive edge of clk or when rst_n is low.

### Operation Logic

Idle/Empty: If buffer_valid is 0, ready_in is asserted. New data is latched into buffer_data and buffer_valid is set to 1 when valid_in is high.
Buffered: If buffer_valid is 1, ready_in is deasserted. The buffer holds the data. valid_out remains high.
Consumption: When valid_in goes low, the buffer is considered empty (skid behavior), and buffer_valid is cleared, allowing new data to be accepted in the next cycle if valid_in is high again.

Verification

The testbench (tb/tb_skid_buffer_8bit.v) verifies the following scenarios:

Test Case	Description	Result
TC1	Basic Pass-Through	PASS
TC2	Backpressure (Ready In = 0)	PASS
TC3	Skid Behavior (Immediate Accept)	PASS

### Expected Results

After running the simulation, the Log panel should show:

Simulation ends with INFO: PASS.
INFO: PASS

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