Memory & FIFOs

Simple CAM 4-Entry x 8-Bit — L2 Upgrade

Simple CAM 4-Entry x 8-Bit with search, write, and invalidate operations for L2 cache tag lookup.

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Simple CAM 4-Entry x 8-Bit — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a synchronous Content-Addressable Memory (CAM) with 4 entries and an 8-bit data width.

It supports search, write, and invalidate operations.

The module is designed for low-latency associative memory tasks, such as L2 cache tag lookup, where parallel comparison is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for Simple CAM 4-Entry x 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Simple CAM 4-Entry x 8-Bit with search, write, and invalidate operations for L2 cache tag lookup.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4 Independent Entries: Stores 8-bit data per entry.
Synchronous Interface: All operations (Search, Write, Invalidate) occur on the rising edge of the clock.
Search: Compares input data against all valid entries simultaneously.
Write: Updates a specific entry index with new data and marks it as valid.
Invalidate: Marks a specific entry as invalid, preventing it from matching during search.
Low Complexity: Minimal logic overhead, suitable for resource-constrained environments.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`cmd`	Input	2	Command: `2'b00`=Search, `2'b01`=Write, `2'b10`=Invalidate
`data_in`	Input	8	Data input for search or write
`addr_in`	Input	8	Address input (uses `[1:0]` for entry index)
`data_out`	Output	8	Matched data output (valid when `hit` is high)
`hit`	Output	1	Hit flag indicating a match was found
`hit_idx`	Output	2	Index of the matched entry

Architecture

The module consists of a memory array (entries), a validity register array (valid), a comparator block, and a control logic block.

Search: On cmd=00, the comparator checks data_in against all entries where valid[i] == 1. If a match is found, hit is asserted, and hit_idx/data_out are updated.
Write: On cmd=01, the data at addr_in[1:0] is updated, and the corresponding valid bit is set to 1.
Invalidate: On cmd=10, the valid bit at addr_in[1:0] is set to 0.

Verification

The testbench covers the following scenarios to ensure correctness:

Test Case	Description	Expected Result
TC1	Write 0xAA to index 0 and search	Hit at index 0
TC2	Invalidate index 0 and search	No hit
TC3	Write 0xBB to index 1 and 0xCC to index 2	Hits at indices 1 and 2
TC4	Invalidate indices 1 and 2	No hit
TC5	Reset and write 0xFF to index 3	Hit at index 3

All test cases passed successfully in the simulation log.

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