Memory & FIFOs

Credit-Based Ready Flow Control (4)

A credit-based flow control module that manages ready/valid handshakes with a maximum of 4 credits.

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Credit-Based Ready Flow Control (4) is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a credit-based flow control mechanism to manage data transfer between a sender and a receiver.

It supports a maximum of 4 concurrent outstanding transactions.

The module enforces backpressure by deasserting the ready signal when the credit count reaches zero, preventing sender overflow.

Choose Open in IDE. RTL Studio loads the packaged workspace for Credit-Based Ready Flow Control (4).
Read the Verilog module in the editor. The catalog line for this block: A credit-based flow control module that manages ready/valid handshakes with a maximum of 4 credits.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Bounded Buffering: Supports up to 4 concurrent outstanding transactions.
Backpressure: Automatically stops the sender when credits are exhausted.
Credit Management: Decrement on send, increment on receiver acceptance.
Monitoring: Exposes current credit count for system monitoring.
Synchronous Logic: Simple synchronous design with asynchronous reset.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`valid_i`	Input	1	Valid signal from the sender
`ready_o`	Output	1	Ready signal to the sender (high if credits > 0)
`data_valid_i`	Input	1	Valid signal from the receiver side (data available)
`data_ready_o`	Output	1	Ready signal to the receiver (always 1)
`credits_avail_o`	Output	4	Current number of available credits (0-4)

Architecture

The module uses a 3-bit register (credit_cnt) to track the credit count. The counter initializes to 4 upon reset.

Decrement: Credits are decremented when the sender fires (valid_i && ready_o) AND the receiver does NOT accept data (!data_valid_i).
Increment: Credits are incremented when the receiver accepts data (data_valid_i && data_ready_o) AND the sender did NOT fire (!valid_i).
No Change: If both sender and receiver handshake simultaneously, the credit count remains unchanged.
Backpressure: ready_o is asserted high only when credit_cnt > 0.

Verification

The testbench verifies five key scenarios to ensure correct behavior:

Reset State: Verifies initial credit count is 4.
Credit Draining: Verifies credits decrease to 0 as data is sent.
Backpressure: Verifies ready_o is deasserted when credits are 0.
Credit Refill: Verifies credits increase when the receiver accepts data.
Ready State: Verifies ready_o is asserted when credits are available.

### Test Results

Test Case	Description	Result
TC1	Initial credits should be 4	PASS
TC2	Credits drained to 0	PASS
TC3	Backpressure active when credits=0	PASS
TC4	Credits refilled to 4	PASS
TC5	Ready active when credits > 0	PASS

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