Memory & FIFOs

Dual-Port Register File 4x16 — L2 Upgrade

Dual-Port Register File 4x16 with Invalidate, Shadow Commit, Byte Enable, and Hazard Detection for L2 upgrades.

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Dual-Port Register File 4x16 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a high-performance dual-port register file with 4 entries and a 16-bit data width. It is designed for integration into RISC-V cores, specifically for L2 cache or register file upgrades. Key features include independent read/write ports, byte-enable support, atomic shadow commit mechanisms, and robust hazard detection to prevent read-after-write conflicts.

This IP provides a robust, fully verified dual-port register file with advanced control features including atomic shadow commits and hazard detection. It is ready for integration into RISC-V cores requiring L2 cache or register file upgrades.

Choose Open in IDE. RTL Studio loads the packaged workspace for Dual-Port Register File 4x16 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Dual-Port Register File 4x16 with Invalidate, Shadow Commit, Byte Enable, and Hazard Detection for L2 upgrades.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Dual Independent Ports: Port A and Port B support simultaneous read and write operations.
Configurable Depth/Width: 4 entries, 16-bit data width.
Byte-Enable Support: Partial word writes via be_a and be_b signals.
Invalidate Control: Signals inv_a and inv_b to clear specific register entries.
Shadow Commit Mechanism: Buffered writes in shadow memory are applied atomically to main memory via commit_shadow.
Hazard Detection: Outputs hazard_a and hazard_b to indicate read-after-write conflicts, allowing backpressure or stalling.
Synchronous Reset: Clears all internal state (main and shadow memory) on reset.

Ports

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`wa_a`	Input	2	Port A write address [1:0]
`we_a`	Input	1	Port A write enable
`wd_a`	Input	16	Port A write data [15:0]
`be_a`	Input	2	Port A byte enable [1:0] (0:LSB, 1:MSB)
`inv_a`	Input	1	Port A invalidate control
`rb_a`	Input	2	Port A read address [1:0]
`rd_a`	Output	16	Port A read data [15:0]
`wb_b`	Input	2	Port B write address [1:0]
`we_b`	Input	1	Port B write enable
`wd_b`	Input	16	Port B write data [15:0]

Architecture

The module consists of two memory arrays: mem (main) and shadow_mem (buffer).

Write Operation: When we_a or we_b is asserted, data is written to shadow_mem and marked valid. Byte enables allow selective updates.
Invalidate: If inv_a or inv_b is asserted, the corresponding entry in mem is cleared, and the shadow entry is invalidated.
Commit: When commit_shadow is asserted, valid entries from shadow_mem are copied to mem.
Hazard Detection: If a write address on one port matches the read address on the other port during the same cycle, the respective hazard output is asserted. In this case, the reading port returns 0 instead of stale data.

Verification

The design has been verified using a comprehensive testbench covering:

Basic read/write operations for both ports.
Byte-enable functionality (partial word writes).
Invalidate logic (clearing entries).
Hazard detection (read-after-write conflicts).
Shadow commit (atomic updates).
Reset behavior.

All 7 test cases pass successfully.

Test Case	Description	Result
TC1	Basic Write and Read Port A	PASS
TC2	Basic Write and Read Port B	PASS
TC3	Byte Enable Port A	PASS
TC4	Invalidate Port A	PASS
TC5	Hazard Detection Port A	PASS
TC6	Shadow Commit	PASS
TC7	Reset	PASS

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