Memory & FIFOs

FWFT Sync FIFO 16x8 — L2 Upgrade

First-Word-Fall-Through synchronous FIFO with 16x8 depth and programmable almost-full/empty thresholds.

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FWFT Sync FIFO 16x8 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a First-Word-Fall-Through (FWFT) synchronous FIFO with a depth of 16 and an 8-bit data width. Unlike standard FIFOs, the FWFT architecture allows data to be read on the same cycle it is written when the FIFO is empty, reducing latency for streaming applications.

Key features include:

Low Latency: Immediate data availability on the first write.
Configurable Flow Control: Programmable almost_full and almost_empty thresholds.
Synchronous Design: Single clock domain with active-low reset.
Educational Focus: Designed for Level 2 complexity, suitable for learning and integration.

Choose Open in IDE. RTL Studio loads the packaged workspace for FWFT Sync FIFO 16x8 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: First-Word-Fall-Through synchronous FIFO with 16x8 depth and programmable almost-full/empty thresholds.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

FWFT Architecture: Data is available at rd_data immediately upon write if the FIFO was previously empty.
Synchronous Operation: Operates with a single clock (clk) and active-low reset (rst_n).
Programmable Thresholds:

- af_thresh: Configurable almost-full threshold (distance from full). - ae_thresh: Configurable almost-empty threshold (distance from empty).

Status Flags:

- full: Asserted when FIFO is completely full. - empty: Asserted when FIFO is completely empty. - almost_full: Asserted when remaining space is less than or equal to af_thresh. - almost_empty: Asserted when used space is less than or equal to ae_thresh.

Memory Depth: 16 words x 8 bits.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`wr_en`	Input	1	Write enable
`rd_en`	Input	1	Read enable
`wr_data`	Input	[7:0]	Data to write
`rd_data`	Output	[7:0]	Data read (FWFT or memory)
`full`	Output	1	FIFO is full
`empty`	Output	1	FIFO is empty
`almost_full`	Output	1	FIFO is near full
`almost_empty`	Output	1	FIFO is near empty
`af_thresh`	Input	[3:0]	Almost-full threshold distance
`ae_thresh`	Input	[3:0]	Almost-empty threshold distance

Architecture

The module uses a dual-pointer approach (write and read pointers) combined with a counter to track the number of items in the FIFO. This counter is the primary source for generating status flags.

### FWFT Logic When the FIFO is empty and a write occurs, the data is latched into a temporary register (fwft_data) and a validity flag (fwft_valid) is set. On the next read cycle, this latched data is prioritized over the memory content, ensuring zero-cycle latency for the first word.

### Logic Description

Write Pointer: Increments when wr_en is high and !full.
Read Pointer: Increments when rd_en is high and !empty.
Count Update: Increments on write, decrements on read.
Almost-Full: Asserted when count >= (DEPTH - af_thresh).
Almost-Empty: Asserted when count <= ae_thresh.

Integration

### Instantiation

### Simulation

Clone the repository.
Open your preferred Verilog simulator (e.g., ModelSim, Vivado Simulator).
Compile rtl/fwft_fifo_almost_prog_16x8.v and tb/tb_fwft_fifo.v.
Run the simulation.

Expected Log Output:

Verification

The testbench verifies reset behavior, threshold assertions, and FWFT timing. All tests passed with zero errors.

Test Case	Description	Result
TC1	Reset state checks empty and almost_empty flags	PASS
TC2	Fill to 14 items checks almost_empty de-assertion and almost_full assertion	PASS
TC3	Fill to 16 items checks full flag	PASS
TC4	Read 12 items checks almost_empty de-assertion	PASS
TC5	Read 2 more items checks almost_empty assertion	PASS
TC6	Read remaining items checks empty flag	PASS
TC7	Verify FWFT data availability on first write	PASS

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