Memory & FIFOs

FWFT Sync FIFO with Almost Full/Empty

A First-Word-Fall-Through (FWFT) synchronous FIFO module with configurable almost full and almost empty threshold flags for precise flow control.

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FWFT Sync FIFO with Almost Full/Empty is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a First-Word-Fall-Through (FWFT) synchronous FIFO with configurable almost full and almost empty threshold flags. It provides precise flow control for high-speed data paths, ensuring low latency by making data available immediately upon a valid read enable.

The module supports configurable data width, depth, and threshold levels, making it suitable for buffering data between synchronous clock domains or as a component within asynchronous clock crossing logic.

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Features

First-Word-Fall-Through (FWFT): Data is available on rd_data immediately when rd_en is asserted, provided the FIFO is not empty.
Configurable Parameters: Supports configurable DATA_WIDTH, DEPTH, AF_THRESH (Almost Full Threshold), and AE_THRESH (Almost Empty Threshold).
Precise Flow Control:

- almost_full asserts when the remaining space is less than or equal to AF_THRESH. - almost_empty asserts when the used space is less than or equal to AE_THRESH.

Robust Flag Logic:

- full prevents invalid writes. - empty prevents invalid reads.

Synchronous Reset: Defined initial state with full and empty asserted high upon reset.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`wr_en`	Input	1	Write enable signal
`rd_en`	Input	1	Read enable signal
`wr_data`	Input	`[DATA_WIDTH-1:0]`	Data input to be written
`rd_data`	Output	`[DATA_WIDTH-1:0]`	Data output from the FIFO
`full`	Output	1	High when FIFO is completely full
`empty`	Output	1	High when FIFO is completely empty
`almost_full`	Output	1	High when FIFO is near full (<= AF_THRESH)
`almost_empty`	Output	1	High when FIFO is near empty (<= AE_THRESH)

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset State	`empty` and `full` flags are high
TC2	Fill to Almost Full	`almost_full` asserts at threshold
TC3	Fill to Full	`full` asserts when depth is reached
TC4	Write to Full	Write is ignored, `full` remains high
TC5	Drain to Almost Empty	`almost_empty` asserts at threshold
TC6	Drain to Empty	`empty` asserts when depth is cleared
TC7	Read from Empty	Read is ignored, `empty` remains high

All test cases passed successfully in simulation.

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