Memory & FIFOs
LIFO Stack 8-Bit
Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.
About this block
Simulate it in the Verilog IDE
LIFO Stack 8-Bit is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This repository contains a robust, synchronous Last-In-First-Out (LIFO) stack IP core. It implements an 8-bit data width with a depth of 8 words. The design is optimized for buffering 8-bit data streams in digital systems, featuring comprehensive status flags (full, empty) and deterministic handling of edge cases such as overflow, underflow, and conflicting control signals.
This IP provides a robust, synchronous Last-In-First-Out (LIFO) stack implementation with an 8-bit data width and a depth of 8 words. It is designed for buffering 8-bit data streams in digital systems. The module includes comprehensive status flags (full, empty) and handles edge cases such as overflow, underflow, and conflicting control signals (simultaneous push/pop) safely by rejecting ambiguous operations.
- Choose Open in IDE. RTL Studio loads the packaged workspace for LIFO Stack 8-Bit.
- Read the Verilog module in the editor. The catalog line for this block: Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Depth: 8 words.
- Data Width: 8 bits.
- Interface: Synchronous clock (
clk) and active-low asynchronous reset (rst_n). - Status Flags:
- full: Asserted high when the stack contains 8 items. - empty: Asserted high when the stack contains 0 items.
- Protection:
- Overflow: Push operations are ignored when the stack is full. - Underflow: Pop operations are ignored when the stack is empty.
- Conflict Resolution: Simultaneous push and pop requests are rejected to ensure deterministic state transitions.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Clock input |
rst_n | Input | 1 | Active-low asynchronous reset |
push_en | Input | 1 | Push enable signal |
pop_en | Input | 1 | Pop enable signal |
data_in | Input | [7:0] | Data input for push operation |
data_out | Output | [7:0] | Data output from pop operation |
full | Output | 1 | High when stack is full |
empty | Output | 1 | High when stack is empty |
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