Memory & FIFOs

Ping-Pong Buffer 8x8

An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Ping-Pong Buffer 8x8 is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8x8 ping-pong buffer for double-buffering data streams in FPGA and ASIC designs. It utilizes two independent 8-word deep memory banks to allow simultaneous write and read operations, ensuring data integrity during frame boundaries without complex handshaking.

The design features a synchronous bank-swap mechanism triggered by a frame_pulse, decoupling write and read domains to simplify interface timing. Registered outputs prevent glitches during swap transitions, making it ideal for pipelines requiring continuous data flow with frame synchronization.

Choose Open in IDE. RTL Studio loads the packaged workspace for Ping-Pong Buffer 8x8.
Read the Verilog module in the editor. The catalog line for this block: An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Dual-Bank Architecture: Two independent 8x8 memory banks for simultaneous read/write.
Synchronous Swapping: Bank roles swap on frame_pulse assertion, aligned with the clock edge.
Glitch-Free Output: Registered read data ensures stability during bank transitions.
Low Resource Usage: Simple dual-bank RAM structure with minimal logic overhead.
Easy Integration: Standard synchronous interface compatible with most FPGA/ASIC flows.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
wr_addr	Input	3	Write address [2:0]
rd_addr	Input	3	Read address [2:0]
wr_data	Input	8	Write data [7:0]
wr_en	Input	1	Write enable
rd_en	Input	1	Read enable
frame_pulse	Input	1	Frame swap trigger
rd_data	Output	8	Read data [7:0]

Verification

The testbench (tb_ping_pong_buffer_8x8.v) verifies:

Basic write and read operations for both banks.
Data integrity after bank swapping.
Isolation between banks (writing to one does not affect the other).

All test cases pass with zero errors. The simulation uses Icarus Verilog and generates a VCD file for waveform inspection.

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