Memory & FIFOs

Regfile 1W2R 8x16 — L2 Upgrade

True dual-clock 1-write-2-read register file with 8x16 depth and registered read output.

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About this block

Simulate it in the Verilog IDE

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Regfile 1W2R 8x16 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a true dual-clock 1-write-2-read register file. It provides 8 locations of 16-bit data width. The write port and read port operate on independent clock domains. Both ports support active-low asynchronous reset. The read port uses registered output for timing closure.

This IP is designed for robust L2 cache upgrades where data integrity across independent clock domains is critical.

This IP provides a robust dual-clock register file for L2 cache upgrades.

Choose Open in IDE. RTL Studio loads the packaged workspace for Regfile 1W2R 8x16 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: True dual-clock 1-write-2-read register file with 8x16 depth and registered read output.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Dual Clock Domain: Independent clk_w (write) and clk_r (read) clocks.
Asynchronous Reset: Active-low resets for both write (rst_n_w) and read (rst_n_r) domains.
Registered Output: Read data is registered to simplify timing analysis and ensure stable outputs.
Synchronous Write: Data is written only when w_en is high.
Compact Architecture: Single memory array shared by both ports.

Ports

Port Name	Direction	Width	Description
`clk_w`	Input	1	Write clock domain
`rst_n_w`	Input	1	Write reset (active low)
`w_addr`	Input	3	Write address [2:0]
`w_data`	Input	16	Write data [15:0]
`w_en`	Input	1	Write enable
`clk_r`	Input	1	Read clock domain
`rst_n_r`	Input	1	Read reset (active low)
`r_addr`	Input	3	Read address [2:0]
`r_data`	Output	16	Read data [15:0]

Architecture

The module contains a single memory array shared by both ports. Write operations occur on the positive edge of clk_w. Read operations occur on the positive edge of clk_r. Reset logic is independent for each clock domain.

Integration

### Instantiation

To integrate this IP into your design, instantiate regfile_1w2r_8x16_true_dclock as follows:

### Timing Constraints

Ensure your SDC constraints account for the independent clock domains. Example constraints:

Verification

The testbench verifies the following scenarios:

TC1: Reset values are zero for all addresses.
TC2: Single write and read back operation.
TC3: Multi-address write and read verification.
TC4: Independent clock domain operation.
TC5: Write enable masking correctness.

### Running Simulation

Ensure you have a Verilog simulator installed (e.g., ModelSim, VCS, or Icarus Verilog).
Navigate to the tb/ directory.
Run the simulation script or command:

### Expected Results

After Run Simulation, the Log panel should show:

TC1 PASS - Reset values correct
TC2 PASS - Single write/read correct
TC3 PASS - Multi write/read correct
TC4 PASS - Dual clock operation correct
TC5 PASS - Write enable masking correct
Simulation ends with INFO: PASS

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