Memory & FIFOs

Regfile Shadow Buffer with Commit

An 8x16 register file with shadow buffer support for speculative writes, atomic commit, and abort capabilities.

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Regfile Shadow Buffer with Commit is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-entry, 16-bit register file with a shadow buffer mechanism to support speculative execution in out-of-order pipelines.

It allows writes to be staged in a shadow buffer without affecting the architectural state until an atomic commit is issued.

An abort signal can discard all speculative writes.

Choose Open in IDE. RTL Studio loads the packaged workspace for Regfile Shadow Buffer with Commit.
Read the Verilog module in the editor. The catalog line for this block: An 8x16 register file with shadow buffer support for speculative writes, atomic commit, and abort capabilities.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Capacity: 8 entries, 16 bits per entry.
Speculation Support: Isolates speculative writes from architectural state.
Atomic Commit: Single-cycle transfer of shadow buffer to architectural register file.
Abort Mechanism: Single-cycle clear of shadow buffer.
Reset: Synchronous active-low reset initializes both buffers to zero.
Latency: Single-cycle write and commit latency.

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`addr_w`	Input	[2:0]	Write address (0-7)
`addr_r`	Input	[2:0]	Read address (0-7)
`data_w`	Input	[15:0]	Write data
`we`	Input	1	Write enable (targets shadow buffer)
`commit`	Input	1	Commit shadow buffer to architectural register file
`abort`	Input	1	Abort and clear shadow buffer
`data_r`	Output	[15:0]	Read data (from architectural register file)

Architecture

The design consists of two internal 8x16 register arrays:

Architectural Register File (arch_regfile): Holds the committed state. Reads always access this array.
Shadow Register File (shadow_regfile): Holds speculative writes. Writes target this array.

### Operation Logic

Write: If we is high, data_w is written to shadow_regfile[addr_w].
Read: data_r is driven by arch_regfile[addr_r].
Commit: If commit is high, shadow_regfile is copied to arch_regfile for all indices.
Abort: If abort is high, shadow_regfile is cleared to zero.
Reset: On !rst_n, both arrays are cleared to zero.

### Constraints & Notes

Priority: commit and abort should not be asserted simultaneously. If both are high, commit takes precedence in the current implementation. This is undefined behavior in the spec and should be avoided by the controller.

Verification

The provided testbench (tb_regfile_shadow_commit_8x16.v) verifies three key scenarios:

Test Case	Description	Expected Result
TC1	Shadow write isolation and commit	Shadow writes are not visible on read until commit. After commit, data is visible.
TC2	Abort discards shadow	Shadow data is discarded after abort and not visible after commit.
TC3	Multiple writes and commit	Multiple speculative writes are correctly committed in order.

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