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Memory & FIFOs

Registered ROM 64x8 with Output Enable

A registered Read-Only Memory with 64 words of 8 bits and an active-low output enable signal.

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About this block

Simulate it in the Verilog IDE

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Registered ROM 64x8 with Output Enable is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered Read-Only Memory (ROM) with 64 words of 8 bits. It features an active-low output enable signal (oe_n) to control data availability on the output bus. When oe_n is active (low), the output reflects the ROM data; when inactive (high), the output is driven to 0x00.

The design includes a synchronous register stage that captures data from the ROM lookup only when oe_n is active. This is suitable for simple storage, buffering, or lookup table applications in digital logic designs where controlled output drive is required.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Registered ROM 64x8 with Output Enable.
  2. Read the Verilog module in the editor. The catalog line for this block: A registered Read-Only Memory with 64 words of 8 bits and an active-low output enable signal.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module consists of two main parts:

  1. ROM Initialization: A memory array mem[0:63] is initialized with hardcoded 8-bit values using an initial block in Verilog.
  2. Synchronous Logic: An always block triggered by the positive clock edge (posedge clk) and asynchronous active-low reset (negedge rst_n).

- On reset (rst_n == 0), the output dout is forced to 0x00. - On normal operation, if the output enable is active (oe_n == 0), dout takes the value from mem[addr]. - If output enable is inactive (oe_n == 1), dout is forced to 0x00 (low drive).

Ports

PortDirectionWidthDescription
clkInput1Clock input (rising edge triggered)
rst_nInput1Active-low asynchronous reset
addrInput6Address input (0-63)
oe_nInput1Active-low output enable. High = Drive 0x00, Low = Drive ROM Data
doutOutput8Data output

Verification

The testbench (tb_registered_rom_oe_64x8) verifies the following behaviors:

  1. Reset Behavior: Ensures dout is 0x00 when rst_n is low.
  2. Data Readout: Verifies that reading address 0 yields 0xAA and address 1 yields 0xBB when oe_n is active.
  3. Output Enable Control: Verifies that dout is 0x00 when oe_n is high (inactive).

All test cases passed successfully during simulation with Icarus Verilog.

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