Memory & FIFOs
ROM 16x8 Case Lookup
A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.
About this block
Simulate it in the Verilog IDE
ROM 16x8 Case Lookup is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a read-only memory (ROM) with 16 words of 8 bits each.
The design uses a case statement to map 4-bit addresses to 8-bit data values.
It is a purely combinational circuit with no clock or enable signals.
- Choose Open in IDE. RTL Studio loads the packaged workspace for ROM 16x8 Case Lookup.
- Read the Verilog module in the editor. The catalog line for this block: A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Interface
The module provides a simple address-to-data mapping interface.
| Port | Direction | Width | Description |
|---|---|---|---|
| addr | input | [3:0] | Address input selecting one of 16 words |
| data | output | [7:0] | Data output corresponding to the address |
Architecture
The internal logic uses a case statement for decoding. Each address value from 0 to 15 maps to its own hex value. For example, address 0x0 outputs 0x00 and address 0xF outputs 0x0F.
The output is driven by an internal reg assigned to the output port to ensure correct net assignment in Verilog-2001 compliant simulators. Despite using a reg, the logic remains purely combinational because it is driven by an always @(*) block.
Verification
The testbench performs sequential and random access tests. It checks all 16 addresses for correct data output. Random access tests verify stability at specific addresses. A watchdog timer prevents infinite simulation hangs.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Sequential read 0-15 | PASS |
| TC2 | Random access F, 0, 8 | PASS |
| TC3 | Stability check | PASS |
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