Memory & FIFOs

Dual-Port RAM Write-First Bypass — L2 Upgrade

Dual-Port RAM with write-first bypass on Port A and shadow buffer read with invalidation on Port B.

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Dual-Port RAM Write-First Bypass — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a dual-port RAM designed for low-latency cache-like structures. It features write-first bypass on Port A, allowing immediate data availability during write cycles, and a shadow buffer on Port B to support speculative or cached data reads with invalidation capabilities.

Choose Open in IDE. RTL Studio loads the packaged workspace for Dual-Port RAM Write-First Bypass — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Dual-Port RAM with write-first bypass on Port A and shadow buffer read with invalidation on Port B.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Dual-Port Architecture: Single clock domain (clk) with synchronous reset (rst_n).
Port A (Write-First Bypass):

- Supports byte-enable writes (be_a) for partial word updates. - Immediate data output on data_out_a during write cycles (bypass). - Standard read access when not writing.

Port B (Shadow Read):

- Reads from a shadow buffer if shadow_valid is asserted for the target address. - Supports invalidation of shadow entries via inv_b signal. - Falls back to main memory mem if shadow is invalid. - Outputs valid_b flag indicating if the returned data is from the shadow buffer.

Configurable: Depth and data width can be adjusted via parameters.

Ports

Signal	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`addr_a`	Input	8	Port A address
`data_in_a`	Input	8	Port A write data
`be_a`	Input	2	Port A byte enable (LSB controls byte 0, etc.)
`we_a`	Input	1	Port A write enable
`en_a`	Input	1	Port A enable
`data_out_a`	Output	8	Port A read/bypass data
`addr_b`	Input	8	Port B address
`en_b`	Input	1	Port B enable
`inv_b`	Input	1	Port B invalidate shadow entry at `addr_b`
`data_out_b`	Output	8	Port B read data

Architecture

The module consists of three internal arrays:

Main Memory (mem): Standard storage.
Shadow Memory (shadow): Stores speculative/cached data.
Shadow Valid Array (shadow_valid): Tracks validity of shadow entries.

### Data Flow

Verification

The testbench verifies the following scenarios:

Test Case	Description	Result
TC1	Basic Write and Read Bypass	PASS
TC2	Byte Enable Write/Read	PASS
TC3	Shadow Commit and Read	PASS
TC4	Invalidate Shadow	PASS
TC5	Shadow Update on Write	PASS

Expected Simulation Log:

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