Memory & FIFOs

Stream Skid Buffer 2-Deep 8-bit

A 2-deep skid buffer for 8-bit stream data that handles back-pressure and stalls.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Stream Skid Buffer 2-Deep 8-bit is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a 2-deep skid buffer for 8-bit AXI-stream-like interfaces.

It decouples producer and consumer clock domains by buffering up to two data words.

It ensures data integrity by back-pressuring the producer when the buffer is full and forwarding data to the consumer as soon as it is ready.

Choose Open in IDE. RTL Studio loads the packaged workspace for Stream Skid Buffer 2-Deep 8-bit.
Read the Verilog module in the editor. The catalog line for this block: A 2-deep skid buffer for 8-bit stream data that handles back-pressure and stalls.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design utilizes two internal registers to store incoming data and valid flags. It implements a simple FIFO-like logic with a depth of two. Back-pressure is asserted when both buffer slots are occupied. Data is forwarded to the output as soon as the consumer is ready and data is available.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`in_valid`	Input	1	Input data valid signal
`in_ready`	Output	1	Input ready to accept data
`in_data`	Input	8	Input data bus
`out_valid`	Output	1	Output data valid signal
`out_ready`	Input	1	Output ready to accept data
`out_data`	Output	8	Output data bus

Verification

The testbench verifies basic back-to-back transfers and output stall scenarios. It checks that in_ready correctly reflects buffer occupancy and confirms that out_valid and out_data behave correctly during stalls.

### Test Cases

Test Case	Description	Result
TC1	Back-to-back transfer (no stall)	PASS
TC2	Stall at output (back-to-back input)	PASS

### Simulation Results

After running the simulation, the Log panel should show:

TC1 in_ready PASS
TC1 out_valid PASS
TC1 out_data PASS
TC2 in_ready PASS
TC2 out_valid PASS
TC2 out_data PASS (multiple entries for buffered data)
Simulation ends with INFO: PASS.

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