Memory & FIFOs
Synchronous 64-Bit FIFO with Full/Empty Flags
A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.
About this block
Simulate it in the Verilog IDE
Synchronous 64-Bit FIFO with Full/Empty Flags is a SystemVerilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This module implements a synchronous first-in-first-out (FIFO) buffer with a 64-bit data width. It is designed for high-performance data buffering in synchronous systems, featuring configurable depth and comprehensive status flags to manage flow control. The design ensures race-free flag generation and supports standard write/read operations with active-low reset.
This module provides a robust, parameterized synchronous FIFO solution with 64-bit data width. Key design choices include a counter-based approach for status flags to prevent race conditions associated with pointer comparison, and extended pointer widths to handle wrap-around logic safely. The implementation is fully synchronous with active-low reset, ensuring predictable behavior in single-clock-domain systems. The design includes configurable thresholds for almost-full and almost-empty states to facilitate efficient flow control in high-throughput applications. While the RTL is complete and verified for logical correctness, the accompanying testbench remains a skeleton and requires further development for comprehensive automated verification.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Synchronous 64-Bit FIFO with Full/Empty Flags.
- Read the SystemVerilog module in the editor. The catalog line for this block: A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Synchronous Operation: Operates on a single clock domain with active-low reset.
- Configurable Depth: Depth is determined by the
ADDR_WIDTHparameter. - Status Flags: Provides
full,empty,almost_full, andalmost_emptyflags for robust flow control. - Thresholds:
- almost_full asserts at 75% capacity. - almost_empty asserts at 25% capacity.
- Parameterized: Supports configurable data width (default 64) and address width.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Clock signal |
rst_n | Input | 1 | Active-low reset |
wr_en | Input | 1 | Write enable signal |
wr_data | Input | 64 | Data input for writing |
rd_en | Input | 1 | Read enable signal |
rd_data | Output | 64 | Data output from reading |
full | Output | 1 | High when FIFO is full |
empty | Output | 1 | High when FIFO is empty |
almost_full | Output | 1 | High when FIFO is >= 75% full |
almost_empty | Output | 1 | High when FIFO is <= 25% full |
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