RTL Studio Open IDE

Memory & FIFOs

Synchronous FIFO Depth Calculator (Counter-Based)

A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Synchronous FIFO Depth Calculator (Counter-Based) is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The fifo_depth_calculator module is a lightweight, synchronous digital IP core designed to track the depth of a FIFO buffer without storing the actual data. It maintains an internal 8-bit counter that increments on write enable (wr_en) and decrements on read enable (rd_en).

This module is ideal for:

  • Flow Control: Providing full, empty, and almost_full status flags to manage data producers and consumers.
  • Status Monitoring: Exposing the current depth via the count output for debugging or adaptive logic.
  • Resource Efficiency: Since it does not store data, it consumes minimal FPGA/ASIC resources compared to a full data FIFO.

This IP provides a synchronous FIFO depth calculator using a counter-based approach. It tracks the number of valid items in a buffer without storing the data itself, making it suitable for flow control, status monitoring, and depth-aware logic in digital designs. The module supports configurable almost-full thresholds and provides standard full, empty, and count outputs. It is designed for easy integration, predictable timing, and comprehensive verification.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Synchronous FIFO Depth Calculator (Counter-Based).
  2. Read the Verilog module in the editor. The catalog line for this block: A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Synchronous Operation: All state changes occur on the rising edge of clk.
  • Asynchronous Reset: Active-low rst_n resets the depth counter to zero.
  • Configurable Threshold: An 8-bit input almost_full_thresh allows dynamic adjustment of the "almost full" warning level.
  • 8-Bit Depth: Supports up to 256 entries (0-255).
  • Standard Interface: Provides standard full, empty, and count outputs.

Architecture

The core of the module is a synchronous 8-bit register (cnt). The logic updates cnt based on wr_en and rd_en:

  1. Write Only (wr_en=1, rd_en=0): Increment cnt if not full.
  2. Read Only (wr_en=0, rd_en=1): Decrement cnt if not empty.
  3. Both (wr_en=1, rd_en=1): No change in cnt (simultaneous read/write).
  4. Neither: No change in cnt.

Status flags are derived combinatorially from the current counter value and control signals.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
wr_enInput1Write enable (increment depth)
rd_enInput1Read enable (decrement depth)
almost_full_threshInput8Threshold for almost_full flag
fullOutput1High when FIFO is full and writing
emptyOutput1High when FIFO is empty
almost_fullOutput1High when depth >= threshold
countOutput8Current FIFO depth (0-255)

Verification

The IP includes a comprehensive testbench (tb_fifo_depth_calculator.v) that validates:

  • Reset Behavior: Counter returns to 0 on rst_n assertion.
  • Write Operations: Counter increments correctly on wr_en.
  • Read Operations: Counter decrements correctly on rd_en.
  • Simultaneous Read/Write: Counter remains unchanged when both are asserted.
  • Flag Assertions: full, empty, and almost_full flags are asserted correctly based on counter state.

### Running Simulation

  1. Ensure you have a Verilog simulator installed (e.g., ModelSim, VCS, or Icarus Verilog).
  2. Compile the RTL and testbench:
  3. Run the simulation:
  4. Check the log for INFO: PASS to confirm all test cases passed.
  5. View the waveform using the generated sim/dump.vcd file.

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