Memory & FIFOs

Pointer-Based Sync FIFO with Flush

Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.

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About this block

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Pointer-Based Sync FIFO with Flush is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

Compact single-clock FIFO that detects full and empty by comparing extra-bit read/write pointers rather than maintaining a separate occupancy counter. Control uses w_en / r_en plus full, empty, and read-side valid. A synchronous flush clears pointers and status in one cycle without chip-wide reset.

Default configuration is 32-bit data and depth 16 (parameter DEPTH). Verified with Icarus Verilog.

Use this block for a small on-chip queue where software or hardware may need to drop pending data via flush. Check full before writes and empty / valid before reads.

Choose Open in IDE. RTL Studio loads the packaged workspace for Pointer-Based Sync FIFO with Flush.
Read the Verilog module in the editor. The catalog line for this block: Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Pointer compare full/empty logic (classic small FIFO style).
flush input for fast queue discard.
Enable-style write/read ports (no dedicated wready).
Read valid tied to !empty.
Parameterized depth (default 16) and data width (default 32).

Ports

Port	Direction	Width	Description
`clk`	Input	1	Single clock for read and write
`rst_n`	Input	1	Active-low reset
`flush`	Input	1	Clear FIFO contents
`w_en`	Input	1	Write enable
`w_data`	Input	32	Write data
`full`	Output	1	FIFO full
`valid`	Output	1	Read data valid (`!empty`)
`r_en`	Input	1	Read enable
`r_data`	Output	32	Read data
`empty`	Output	1	FIFO empty

Verification

Test Case	Description	Status
TC1	Single write/read	PASS
TC2	Burst write to full	PASS
TC3	Burst read to empty	PASS
TC4	Back-to-back read/write	PASS
TC5	Flush during active operation	PASS

Simulation: make sim in the IP leaf.

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