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Memory & FIFOs

True Dual-Port RAM 8x8 — L2 Upgrade

True dual-port RAM with independent write and read clock domains, 8 words x 8 bits, synchronous reset.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

True Dual-Port RAM 8x8 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a True Dual-Port RAM with a depth of 8 words and a width of 8 bits. It supports independent clock domains for write (clk_w) and read (clk_r) operations, enabling true concurrent access without port conflicts. The design ensures synchronous access on both ports to avoid latch inference and guarantees stable output data.

It is fully verified, synthesis-ready, and suitable for L2 cache buffers, FIFO implementations, or any logic requiring independent clock domain data transfer.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for True Dual-Port RAM 8x8 — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: True dual-port RAM with independent write and read clock domains, 8 words x 8 bits, synchronous reset.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • True Dual-Port: Independent read and write clocks allow simultaneous operations.
  • Synchronous Logic: Both ports use synchronous logic to prevent latches and timing hazards.
  • Active-Low Reset: Asynchronous reset (rst_n) initializes all memory cells to zero.
  • Registered Output: Read data is registered on the read clock edge for stable timing.
  • Verified: Fully tested for reset, single write/read, overwrite, and boundary conditions.

Ports

Port NameDirectionWidthDescription
clk_wInput1Write clock domain
clk_rInput1Read clock domain
rst_nInput1Active-low asynchronous reset
addr_wInput[2:0]Write address bus (0-7)
addr_rInput[2:0]Read address bus (0-7)
data_inInput[7:0]Write data bus
weInput1Write enable signal (high = write)
data_outOutput[7:0]Read data bus

Architecture

The internal structure consists of an 8x8 memory array accessed by two independent ports. The write port updates memory synchronously with clk_w, while the read port samples memory synchronously with clk_r.

### Clock Domains

  • Write Path: Controlled by clk_w. Data is written to mem[addr_w] when we is high.
  • Read Path: Controlled by clk_r. Data is sampled from mem[addr_r] and registered to data_out.
  • Reset: rst_n is asynchronous and affects both ports, initializing memory and output register to 0.

Verification

The testbench validates the following scenarios:

  • TC1: Reset behavior ensures all memory cells are zero.
  • TC2: Single write and read cycle confirms data integrity.
  • TC3: Overwrite capability ensures previous data is replaced.
  • TC4: Independent port isolation confirms no cross-talk between clocks.
  • TC5: Boundary address access (0 and 7) verifies full range utilization.

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