Memory & FIFOs

Write-Priority Regfile 4x8 — L2 Upgrade

4-word by 8-bit register file with write-priority, bit-masking, hold, and park controls.

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Write-Priority Regfile 4x8 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4-word by 8-bit register file with advanced write-priority logic.

It features two write ports (Port B: High Priority, Port C: Low Priority) and one read port (Port A).

Key features include bit-level write masking, deterministic priority arbitration, and control modes for 'Hold' (freeze writes) and 'Park' (redirect Port C to address 0).

Choose Open in IDE. RTL Studio loads the packaged workspace for Write-Priority Regfile 4x8 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 4-word by 8-bit register file with write-priority, bit-masking, hold, and park controls.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The register file contains four 8-bit registers. Read access is purely combinational. Write operations occur on the positive clock edge.

### Port Definitions

Port A (Read): Combinational read access. No enable signal required.
Port B (Write High): High-priority write port. Always takes precedence over Port C.
Port C (Write Low): Low-priority write port. Suppressed if Port B writes to the same address.

### Control Modes

Hold Mode (hold_en): Freezes all write operations. The register file state remains unchanged.
Park Mode (park_en): Forces Port C writes to address 0, regardless of the wr_addr_c input. Port B is unaffected.

### Priority Logic If Port B and Port C target the same address in the same cycle:

Port B write is executed.
Port C write is suppressed.

Ports

Signal	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`rd_addr_a`	Input	2	Read address for Port A
`rd_data_a`	Output	8	Read data from Port A
`wr_addr_b`	Input	2	Write address for Port B
`wr_data_b`	Input	8	Write data for Port B
`wr_mask_b`	Input	8	Write mask for Port B (1=write, 0=no-op)
`wr_en_b`	Input	1	Write enable for Port B
`wr_addr_c`	Input	2	Write address for Port C
`wr_data_c`	Input	8	Write data for Port C
`wr_mask_c`	Input	8	Write mask for Port C (1=write, 0=no-op)
`wr_en_c`	Input	1	Write enable for Port C

Verification

The testbench covers six key scenarios. Basic write and read operations are verified for both ports. Write priority is confirmed when both ports target the same address. Bit masking functionality is tested with partial masks. Hold enable is verified to prevent state updates. Park enable is verified to redirect Port C writes to address 0.

Test Case	Description	Result
TC1	Basic Write Port B	PASS
TC2	Basic Write Port C	PASS
TC3	Write Priority (B overrides C)	PASS
TC4	Bit Masking	PASS
TC5	Hold Enable	PASS
TC6	Park Enable	PASS

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