Shift & Bit Manipulation

Arithmetic Right Shift 8-Bit — L1 Upgrade

Arithmetic right shift module with Valid/Ready handshake for 8-bit signed data.

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Arithmetic Right Shift 8-Bit — L1 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a synchronous 8-bit arithmetic right shift operation. It accepts signed 8-bit data via a Valid/Ready handshake interface and shifts the data right by 1 bit, replicating the most significant bit (sign bit) to preserve the signed value.

The design is classified as an L1 Upgrade difficulty level, suitable for basic digital logic integration.

Choose Open in IDE. RTL Studio loads the packaged workspace for Arithmetic Right Shift 8-Bit — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Arithmetic right shift module with Valid/Ready handshake for 8-bit signed data.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

The module uses a synchronous interface with active-high clock and active-low reset. It supports a simplified Valid/Ready handshake where the ready_in signal is always asserted (hardwired to 1), indicating the module is always ready to accept new data on the next clock cycle.

Signal Name	Direction	Width	Description
clk	Input	1	Clock signal
rst_n	Input	1	Active-low reset
valid_in	Input	1	Input data valid
ready_in	Output	1	Input ready (Always 1)
data_in	Input	8	Input data [7:0]
valid_out	Output	1	Output data valid
data_out	Output	8	Output data [7:0]

Architecture

The design consists of a sequential register block that captures input data when valid_in is high. On the rising edge of the clock, the input data is shifted right arithmetically. The sign bit (data_in[7]) is replicated into the new MSB position (data_out[7]), while bits [7:1] are shifted into [6:0]. The output valid_out is asserted when valid data is present in the output register.

Verification

The testbench verifies six specific test cases covering positive numbers, negative numbers, zero, and signal behavior. All tests passed successfully in simulation.

Test Case	Input Hex	Expected Output	Result
TC1: Positive Shift	0x15	0x0A	PASS
TC2: Negative Shift	0xFB	0xFD	PASS
TC3: Zero Shift	0x00	0x00	PASS
TC4: Positive Max	0x3F	0x1F	PASS
TC5: Negative Min	0xC0	0xE0	PASS
TC6: Ready Signal	N/A	1'b1	PASS

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