Shift & Bit Manipulation

16-Bit Bidirectional Shift Register (L/R + Load)

16-bit register with mutually exclusive modes: parallel load, shift left, and shift right.

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About this block

Simulate it in the Verilog IDE

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16-Bit Bidirectional Shift Register (L/R + Load) is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP provides a 16-bit shift register with parallel load capability. It supports synchronous reset and multiple operating modes. The module is implemented in Verilog and verified with Icarus Verilog.

This document describes the 16-bit shift register with parallel load functionality. The module supports synchronous reset and multiple operating modes. Verification confirms correct behavior for all defined test cases.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Bidirectional Shift Register (L/R + Load).
Read the Verilog module in the editor. The catalog line for this block: 16-bit register with mutually exclusive modes: parallel load, shift left, and shift right.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit data width.
Synchronous active-low reset.
Shift Right mode with serial input at MSB.
Shift Left mode with serial input at LSB.
Parallel Load mode for immediate data update.
Hold mode to maintain current state.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Synchronous reset, active low
mode_shift_right	Input	1	Enable shift right operation
mode_shift_left	Input	1	Enable shift left operation
mode_parallel_load	Input	1	Enable parallel load operation
data_in	Input	1	Serial data input
parallel_data_in	Input	[15:0]	Parallel data input
data_out	Output	[15:0]	Shift register output

Verification

The testbench covers five key scenarios. Reset initializes the register to zero. Parallel load updates the register with a 16-bit value. Shift right moves bits toward LSB with serial input at MSB. Shift left moves bits toward MSB with serial input at LSB. Hold mode preserves the current register value. All tests passed successfully in simulation.

Test Case	Description	Result
TC1	Reset to zero	PASS
TC2	Parallel load 0xA5A5	PASS
TC3	Shift right 4 cycles	PASS
TC4	Shift left 4 cycles	PASS
TC5	Hold state	PASS

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