Shift & Bit Manipulation

8-Bit Parallel-to-Serial Converter

Converts 8-bit parallel input to LSB-first serial output with busy flag and synchronous load.

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About this block

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8-Bit Parallel-to-Serial Converter is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core converts an 8-bit parallel input into a serial bitstream. It shifts data out least-significant-bit (LSB) first on each clock cycle. The design uses a synchronous shift register with a 4-bit counter for tracking. A busy_o signal indicates when the core is actively shifting data.

This 8-bit parallel-to-serial converter provides a simple and reliable way to serialize data. It supports LSB-first output and includes a busy flag for system integration. The design is fully synchronous except for the active-low reset. Integrators can use this core for basic serial communication protocols or data packing tasks.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Parallel-to-Serial Converter.
Read the Verilog module in the editor. The catalog line for this block: Converts 8-bit parallel input to LSB-first serial output with busy flag and synchronous load.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Converts 8-bit parallel data to serial output.
LSB-first shifting order.
Synchronous load and enable control.
Active-low asynchronous reset.
Busy flag for flow control.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`load_i`	Input	1	Load parallel data into shift register
`en_i`	Input	1	Enable shifting when busy
`parallel_i`	Input	8	Parallel data input
`s_o`	Output	1	Serial data output
`busy_o`	Output	1	High during shifting operation

Architecture

The module consists of an 8-bit shift register and a 4-bit counter. Data is loaded into the shift register when load_i is asserted. The busy_o signal goes high immediately after loading. Shifting occurs only when busy_o is high and en_i is asserted. Each clock cycle, the LSB is output and the register shifts right. The counter increments until it reaches 7, at which point busy_o deasserts.

Verification

The testbench includes five self-checking test cases. It verifies correct shifting for 0xFF, 0x00, 0xAA, and 0x55. It also tests reset behavior during an active shift operation. All tests passed successfully in the simulation log.

Test Case	Description	Result
TC1	Load 0xFF and shift out	PASS
TC2	Load 0x00 and shift out	PASS
TC3	Load 0xAA and shift out	PASS
TC4	Load 0x55 and shift out	PASS
TC5	Reset during shift	PASS

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