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Shift & Bit Manipulation

8-Bit Uni-Dir Shift Register (Load + SI) — L1 Upgrade — L2 Upgrade

8-Bit unidirectional shift register with parallel load and serial input support for logical and arithmetic shift-right operations.

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8-Bit Uni-Dir Shift Register (Load + SI) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit unidirectional shift register with parallel load capability.

It supports both logical and arithmetic shift-right operations, controlled by a mode select signal.

The design is fully synthesizable, latch-free, and compliant with Verilog-2001 standards.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Uni-Dir Shift Register (Load + SI) — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 8-Bit unidirectional shift register with parallel load and serial input support for logical and arithmetic shift-right operations.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Data Width: 8 bits.
  • Operations:

- Parallel Load (High Priority). - Shift Right (Logical or Arithmetic).

  • Control Signals:

- load: Parallel load enable. - shift_en: Shift enable. - arith_mode: Selects between Logical (0) and Arithmetic (1) shift.

  • Reset: Asynchronous active-low reset.
  • Clock: Synchronous positive-edge triggered.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
loadInput1Parallel load enable (High Priority)
shift_enInput1Shift enable (Active when load is low)
arith_modeInput1Shift mode select (1=Arithmetic, 0=Logical)
serial_inInput1Serial data input for Logical Shift MSB
parallel_inInput[7:0]Parallel data input for Load operation
qOutput[7:0]Shift register output

Architecture

The module utilizes a single always block triggered on the positive edge of clk or the negative edge of rst_n.

  1. Reset: When rst_n is low, the output q is forced to zero.
  2. Load: If load is high, parallel_in is latched into q, overriding any shift operation.
  3. Shift: If load is low and shift_en is high, the register shifts right:

- Arithmetic Mode: The MSB (q[7]) is replicated into the new MSB position. - Logical Mode: The serial_in signal is injected into the new MSB position.

  1. Hold: If neither load nor shift_en is active, the current value is held.

### Block Diagram

Verification

The provided testbench covers the following scenarios:

  • Asynchronous Reset
  • Parallel Load
  • Logical Shift Right (with serial_in = 1 and 0)
  • Arithmetic Shift Right (Positive and Negative MSB)
  • Hold State

All test cases are designed to pass successfully in simulation. To run the verification:

  1. Open your preferred HDL simulator.
  2. Compile the RTL file: rtl/shift_register_8bit_unidir_load_si_arithmetic_mode_serial_in_arith.v
  3. Compile the testbench: tb/tb_shift_register_8bit_unidir_load_si_arithmetic_mode_serial_in_arith.v
  4. Run the simulation and check the log for INFO: PASS.

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