Shift & Bit Manipulation

Nibble Interleave / Deinterleave 16-bit — L2 Upgrade

A 16-bit nibble interleave module that reverses nibble order with skid buffer support for backpressure handling.

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Nibble Interleave / Deinterleave 16-bit — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust nibble interleaving solution for 16-bit data paths. It handles backpressure gracefully using a skid buffer. The design is simple and easy to integrate into larger systems. It is suitable for applications requiring data reordering.

This IP implements a 16-bit nibble interleave (reverse) function, rearranging four 4-bit nibbles from input order (N3 N2 N1 N0) to output order (N0 N1 N2 N3). It supports backpressure via a skid buffer for flow control and is designed for L2 difficulty verification and synthesis.

The design is fully synchronous with an active-low reset and has been verified using Icarus Verilog.

Choose Open in IDE. RTL Studio loads the packaged workspace for Nibble Interleave / Deinterleave 16-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit nibble interleave module that reverses nibble order with skid buffer support for backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Nibble Reversal: Reverses nibble order in a 16-bit data word (N3N2N1N0 -> N0N1N2N3).
Flow Control: Supports valid/ready handshaking protocol.
Backpressure Handling: Includes a skid buffer to hold data when the output is not ready.
Synchronous Design: Fully synchronous with active-low reset.
Verification: Verified with Icarus Verilog testbench covering basic functionality and backpressure scenarios.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
in_valid	Input	1	Input data valid signal
in_data	Input	16	Input data bus
in_ready	Output	1	Input ready signal
out_valid	Output	1	Output data valid signal
out_data	Output	16	Output data bus
out_ready	Input	1	Output ready signal

Architecture

The design uses a three-state finite state machine (FSM).

IDLE: Waits for valid input data.
SHIFT: Prepares the data for output by shifting/rotating nibbles.
OUTPUT: Drives the output valid signal.

A skid buffer stores data when the output is not ready (out_ready is low). The output data is generated combinatorially from either the shift register (if no skid data) or the skid buffer (if data is pending).

Verification

The testbench verifies basic functionality and backpressure handling. It checks nibble reversal for various input patterns and ensures the skid buffer correctly holds data during backpressure, resuming correctly after backpressure is released.

### Test Cases

Test Case	Description	Expected Result	Status
TC1	Basic Nibble Reverse	0xABCD -> 0xDCBA	PASS
TC2	Skid Buffer Backpressure	Data held until out_ready	PASS
TC3	Multiple Words	0x5678 -> 0x8765	PASS
TC4	Zero Input	0x0000 -> 0x0000	PASS
TC5	Skid Overflow	Backpressure on second word	PASS

### Simulation Log

After Run Simulation, the Log panel should show:

TC1 PASS out_data=DCBA
TC2 PASS out_data=4321 (skid pending)
TC2 PASS skid consumed
TC3 PASS out_data=8765
TC4 PASS out_data=0000
TC5a PASS in_ready=0 (skid full)
TC5b PASS out_data=AAAA
TC5c PASS out_data=BBBB

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