Shift & Bit Manipulation

32-Bit Funnel Shifter

A combinational 32-bit funnel shifter that concatenates two 32-bit inputs and shifts them left to extract a 32-bit window.

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About this block

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32-Bit Funnel Shifter is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 32-bit funnel shifter for unaligned data access. It is commonly used in load/store units to handle data that crosses 32-bit word boundaries.

This IP provides a combinational funnel shifter for 32-bit data. It concatenates two 32-bit inputs (hi and lo) into a 64-bit stream, performs a logical left shift, and extracts the upper 32 bits as the output.

The design is verified for standard shift ranges (0-31) and edge cases (>=32).

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Funnel Shifter.
Read the Verilog module in the editor. The catalog line for this block: A combinational 32-bit funnel shifter that concatenates two 32-bit inputs and shifts them left to extract a 32-bit window.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module operates as follows:

Concatenation: hi and lo are concatenated into a 64-bit vector {hi, lo}.
Shifting: The 64-bit vector is logically shifted left by the shift amount (0-31).
Extraction: Bits [63:32] of the shifted result are selected as the 32-bit output.

Note on Shift Amounts:

Shifts 0-31 perform standard funnel shifting.
Shifts >= 32 effectively discard the hi input. The output corresponds to the lo input shifted left by (shift - 32) bits, with zeros filling the lower bits.

Ports

Port	Direction	Width	Description
hi	Input	32	Upper 32 bits of input stream
lo	Input	32	Lower 32 bits of input stream
shift	Input	5	Shift amount (0-31 recommended, >=32 supported)
out	Output	32	Shifted 32-bit result

Verification

The testbench validates the shifter against a golden model. It checks shift amounts of 0, 1, 31, 32, and 33, as well as edge cases with all zeros and all ones.

### Test Cases

Test Case	Shift	Description	Result
TC1	0	Output equals `hi`	PASS
TC2	1	Output equals `{hi[30:0], lo[31]}`	PASS
TC3	31	Output equals shifted `lo` boundary	PASS
TC4	32	Output equals `lo` (shifted by 0)	PASS
TC5	33	Output equals `lo` shifted left by 1	PASS
TC6	16	Random values (all 1s and all 0s)	PASS

### Simulation Output

After running the simulation, the Log panel should display:

TC1 PASS - Shift 0 correct
TC2 PASS - Shift 1 correct
TC3 PASS - Shift 31 correct
TC4 PASS - Shift 32 correct
TC5 PASS - Shift 33 correct
TC6 PASS - Random values correct
Simulation ends with INFO: PASS.

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