Shift & Bit Manipulation

8-Bit Bit Reversal (Endianness Independent) — L1 Upgrade

8-Bit Bit Reversal with registered output, enable control, and sticky error flag.

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8-Bit Bit Reversal (Endianness Independent) — L1 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit bit-reversal function with registered output. It is designed to be endianness independent and suitable for Level 1 (L1) cache upgrades or similar data path applications. The design includes an enable control signal and a sticky error flag for robustness.

This IP provides a simple, efficient, and robust 8-bit bit-reversal solution. It is easy to integrate into larger systems, featuring registered output for timing closure and error detection for data integrity. The design is endianness independent and suitable for various digital signal processing and data path applications.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Bit Reversal (Endianness Independent) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit Bit Reversal with registered output, enable control, and sticky error flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Reversal: Reverses the bit order of an 8-bit input vector.
Registered Output: Output is synchronized to the clock edge.
Enable Control: Data is only latched when the en signal is high.
Sticky Error Flag: Asserts if the input data is all zeros (0x00) or all ones (0xFF), indicating a trivial or potentially invalid pattern. Note: This flag is cleared on reset.
Active-Low Reset: Synchronous reset logic for clean initialization.

Architecture

The design consists of two main stages:

Combinational Reversal Stage: Reverses the bit order of data_in.
Registered Output Stage: Latches the reversed data, valid flag, and error flag on the rising edge of clk when en is asserted.

### Block Diagram

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low reset
`en`	Input	1	Enable signal
`data_in`	Input	8	Input data to be reversed
`data_out`	Output	8	Reversed output data
`valid_out`	Output	1	Valid output flag (high when `en` is high)
`err_sticky`	Output	1	Sticky error flag (high if input was all 0s or all 1s)

Verification

The testbench covers the following scenarios:

Test Case	Description	Expected Result
TC1	Basic reversal of `0x01`	`data_out` is `0x80`, `valid_out` is 1, `err_sticky` is 0
TC2	Basic reversal of `0x80`	`data_out` is `0x01`
TC3	Error sticky set for all 0s	`err_sticky` is 1
TC4	Error sticky set for all 1s	`err_sticky` is 1
TC5	Enable deasserted	`valid_out` is 0
TC6	Reset clears everything	`data_out`, `valid_out`, `err_sticky` are 0

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