Shift & Bit Manipulation

Bit-Field Extract 16→8

Extracts an 8-bit field from a 16-bit input word using a barrel shifter and mask.

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About this block

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Bit-Field Extract 16→8 is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a purely combinational module that extracts an 8-bit field from a 16-bit input word.

It utilizes a barrel shifter to align the desired field to the least significant bits, followed by masking logic to isolate the 8-bit output.

This module is ideal for data packing, unpacking, and bit-field extraction tasks in communication protocols where low latency is critical.

Choose Open in IDE. RTL Studio loads the packaged workspace for Bit-Field Extract 16→8.
Read the Verilog module in the editor. The catalog line for this block: Extracts an 8-bit field from a 16-bit input word using a barrel shifter and mask.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`in_word`	Input	16	Input data word containing the field to extract
`offset`	Input	4	Shift amount to align the field (0-15)
`out_field`	Output	8	Extracted 8-bit field

Architecture

The module operates in two stages:

Alignment: A barrel shifter right-shifts the 16-bit input word by the amount specified in offset.
Extraction: The lower 8 bits of the shifted word are assigned to the output.

Verification

The IP has been verified with six test cases covering various offsets and input patterns. The testbench tb/tb_bit_field_extract_16to8.v drives these vectors and checks for mismatches.

### Test Cases

Test Case	Input (`in_word`)	Offset (`offset`)	Expected Output (`out_field`)	Description
TC1	`16'hDEAD`	0	`8'hAD`	Extract LSBs
TC2	`16'hDEAD`	4	`8'hEA`	Extract middle bits
TC3	`16'hDEAD`	8	`8'hDE`	Extract MSBs
TC4	`16'hFFFF`	0	`8'hFF`	All Ones
TC5	`16'h0000`	8	`8'h00`	All Zeros
TC6	`16'hAAAA`	1	`8'h55`	Alternating Pattern

### Running Simulation

Compile the RTL and Testbench.
Run the simulation.
Check the log output for PASS messages.

Expected Log Output:

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