RTL Studio Open IDE

Shift & Bit Manipulation

Bitfield Pack Insert 32-bit

Combinational module to insert a variable-width field into a 32-bit data word at a specified offset.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Bitfield Pack Insert 32-bit is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP provides a robust solution for dynamic bitfield manipulation.

It is optimized for combinational performance without pipeline stages.

Use this module when you need to update specific bit ranges in a 32-bit word dynamically.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Bitfield Pack Insert 32-bit.
  2. Read the Verilog module in the editor. The catalog line for this block: Combinational module to insert a variable-width field into a 32-bit data word at a specified offset.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Variable Field Widths: Supports widths from 0 to 32 bits.
  • Variable Offsets: Supports insertion offsets from 0 to 31 bits.
  • Edge Case Handling: Gracefully handles zero-width fields (no change to output).
  • Combinational Logic: Fully synchronous-free, ensuring minimal latency.

Ports

Port NameDirectionWidthDescription
data_inInput32Input data word to be modified
field_inInput32Field value to insert
offsetInput5Bit position where the field starts (0-31)
widthInput5Number of bits to insert (0-32)
data_outOutput32Modified data word

Verification

The testbench covers five key scenarios to ensure correctness:

  1. TC1: Inserts an 8-bit field at offset 0.
  2. TC2: Inserts a 4-bit field at offset 12.
  3. TC3: Inserts a 16-bit field at offset 16.
  4. TC4: Inserts a 1-bit field at offset 31.
  5. TC5: Verifies that a 0-width field results in no change to the output.

All test cases passed successfully in the simulation log.

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