Shift & Bit Manipulation

Funnel Shift Merge 16-bit — L2 Upgrade

A single-slot valid/ready handshake buffer for 16-bit data with backpressure support.

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Funnel Shift Merge 16-bit — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a single-slot valid/ready handshake buffer for 16-bit data.

It merges upstream valid signals into a downstream valid stream.

The module asserts ready_in only when the internal register is empty.

Choose Open in IDE. RTL Studio loads the packaged workspace for Funnel Shift Merge 16-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A single-slot valid/ready handshake buffer for 16-bit data with backpressure support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports 16-bit parallel data transfer.
Implements standard valid/ready handshake protocol.
Asynchronous reset for safe initialization.
Low latency single-cycle data path.
Prevents data loss during backpressure scenarios.

Ports

Port	Direction	Width	Description
clk	input	1	Clock signal
rst_n	input	1	Active-low reset
valid_in	input	1	Upstream data valid
data_in	input	16	Upstream data bus
ready_in	output	1	Upstream ready signal
valid_out	output	1	Downstream data valid
data_out	output	16	Downstream data bus

Architecture

The following diagram illustrates the data flow and control logic.

The internal register holds the data until valid_out is asserted. Ready_in is driven by the inverse of the valid_reg flag. This ensures the upstream source cannot overwrite uncommitted data.

Verification

The testbench covers reset behavior and data transfer scenarios. It verifies backpressure handling when the buffer is full. It checks data integrity across multiple transfer cycles. It ensures reset clears the state even during active transfer.

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Single Transfer	PASS
TC3	Backpressure Init	PASS
TC4	Stream Word 1	PASS
TC5	Invalid Data Handling	PASS
TC6	Reset During Transfer	PASS

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