Shift & Bit Manipulation

8-Bit Byte-Swap (Endianness Converter) — L1 Upgrade

Registered 8-bit byte-swap module with enable and valid handshake for endianness conversion.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

8-Bit Byte-Swap (Endianness Converter) — L1 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a registered data path module for 8-bit data. It functions as a valid handshake synchronizer with an enable signal and asynchronous reset. For 8-bit widths, the data path acts as a buffer, ensuring that the valid_out signal is registered and synchronized with the clock domain.

This IP provides a simple registered interface for 8-bit data. It ensures synchronized valid signals for pipeline stages by registering both the data and the valid handshake signal. The design is suitable for L1 upgrade paths or any stage requiring a single-cycle delay with enable control.

Key Characteristics:

Data Width: 8-bit
Reset Type: Asynchronous, Active-Low
Enable: Synchronous gating of data capture
Handshake: Valid-only (no Ready signal)

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Byte-Swap (Endianness Converter) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-bit byte-swap module with enable and valid handshake for endianness conversion.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Asynchronous Reset: Supports active-low rst_n for immediate initialization.
Enable Control: Includes an enable signal en to stall data propagation without resetting state.
Valid Handshake: Ensures data is only captured when valid_in is asserted.
Registered Output: Provides stable timing for downstream logic by registering both data (dout) and valid (valid_out) signals.

Ports

Port Name	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Active-low asynchronous reset
en	input	1	Enable signal to allow data capture
din	input	8	Input data bus
valid_in	input	1	Valid input handshake signal
valid_out	output	1	Registered valid output signal
dout	output	8	Registered output data bus

Architecture

The module uses a single clock edge to register both data and valid signals. The enable signal gates the data capture path. The valid output is driven by a registered state bit.

If rst_n is low, dout and valid_out are cleared.
If rst_n is high and en is high:

- If valid_in is high, dout updates to din and valid_out becomes high. - If valid_in is low, valid_out becomes low (data holds previous value).

If en is low, valid_out is forced low, and dout holds its value.

Verification

The testbench covers reset behavior, enable stalling, and valid handshake timing. It verifies data pass-through for multiple transactions and checks that valid_out remains low when valid_in is low.

Test Case	Description	Result
TC1	Basic Pass-Through with Valid Handshake	PASS
TC2	Enable Low (Stall)	PASS
TC3	Reset Behavior	PASS
TC4	Multiple Transactions	PASS
TC5	Invalid Input Handling	PASS

More in Shift & Bit Manipulation

All Shift & Bit Manipulation blocks