Shift & Bit Manipulation

8-Bit Barrel (Shift/Rotate × Left/Right) — L1 Upgrade — L2 Upgrade

8-bit registered barrel shifter and rotator with support for logical, arithmetic, and serial shift modes.

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About this block

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8-Bit Barrel (Shift/Rotate × Left/Right) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a flexible 8-bit shift and rotate unit with registered outputs. It is designed for datapath applications requiring precise timing control via synchronous updates.

### Key Features

Registered Output: Outputs update on the clock edge, ensuring timing closure.
Multiple Modes: Supports 8 distinct operations including rotation, logical/arithmetic shifts, and serial shifts.
Synchronous Load: Allows parallel loading of data into the shift register.
Asynchronous Reset: Active-low reset forces output to zero.
Sign Preservation: Arithmetic shifts preserve the sign bit (MSB).
Fixed Step: Operates as a 1-bit shift per clock cycle. The shift_amt input is present for interface compatibility but is unused in this specific registered implementation.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Barrel (Shift/Rotate × Left/Right) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit registered barrel shifter and rotator with support for logical, arithmetic, and serial shift modes.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`mode`	Input	3	Operation mode selector
`shift_amt`	Input	3	Unused: Fixed 1-bit step implementation. Kept for interface consistency.
`serial_in`	Input	1	Serial data input for shift operations
`load`	Input	1	Synchronous load enable
`data_in`	Input	8	Parallel data input
`data_out`	Output	8	Shifted or rotated data output

Verification

The testbench verifies all 8 modes plus load and reset functionality. Simulation uses Icarus Verilog. All 10 test cases pass successfully.

Test Case	Description	Expected Result	Status
TC1	Rotate Left 1	0x55	PASS
TC2	Rotate Right 1	0xAA	PASS
TC3	Shift Left Logical 1	0x54	PASS
TC4	Shift Right Logical 1	0x2A	PASS
TC5	Shift Left Arithmetic 1	0xC0	PASS
TC6	Shift Right Arithmetic 1	0xC0	PASS
TC7	Serial Shift Left	0x01	PASS
TC8	Serial Shift Right	0x80	PASS
TC9	Load Operation	0xFF	PASS
TC10	Reset Operation	0x00	PASS

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