Shift & Bit Manipulation

32-Bit Barrel (Nop / LSL / LSR / ROL)

Combinational 32-bit barrel with op encoding: pass-through, logical left, logical right, and rotate left.

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About this block

Simulate it in the Verilog IDE

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32-Bit Barrel (Nop / LSL / LSR / ROL) is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a fully combinational 32-bit barrel shifter capable of logical shifts and rotate operations. It supports four distinct operation modes controlled by a 2-bit opcode: No-Op, Logical Left Shift, Logical Right Shift, and Rotate Left. The design is optimized for synthesis, using parallel computation and a multiplexer structure to ensure low latency and high performance. It is suitable for integration into datapaths requiring fast bitwise manipulation.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Barrel (Nop / LSL / LSR / ROL).
Read the Verilog module in the editor. The catalog line for this block: Combinational 32-bit barrel with op encoding: pass-through, logical left, logical right, and rotate left.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Width: 32-bit input and output.
Shift Amount: 5-bit input, supporting shifts from 0 to 31.
Operation Modes:

- No Op: Passes input directly to output. - Logical Left Shift (LLS): Shifts left, filling vacated bits with zeros. - Logical Right Shift (LRS): Shifts right, filling vacated bits with zeros. - Rotate Left (RLL): Shifts left with wrap-around behavior.

Architecture: Fully combinational, no clock dependency.
Verification: Includes a comprehensive testbench verifying all modes and edge cases.

Interface

Port Name	Direction	Width	Description
`data`	Input	32	Input data vector
`amount`	Input	5	Shift/Rotate amount (0-31)
`op`	Input	2	Operation selector
`result`	Output	32	Output result vector

Architecture

The module uses a parallel computation structure. It calculates all four possible results simultaneously. A multiplexer selects the final result based on the op signal.

Integration

### Instantiation Example

To instantiate this module in your design, use the following Verilog code:

### Synthesis Notes

The design is fully combinational.
Ensure that amount is within the valid range [0, 31].
The op signal should be driven by a stable value to avoid glitches in the output.
For optimal timing, consider adding pipeline registers if this IP is part of a critical path.

Verification

The design includes a comprehensive testbench (tb/tb_shifter_rotate_32bit.v).

### Running Simulation

Open your preferred Verilog simulator (e.g., ModelSim, Vivado Simulator, Icarus Verilog).
Compile the source file rtl/shifter_rotate_32bit.v and the testbench tb/tb_shifter_rotate_32bit.v.
Run the simulation.

### Test Cases

Test Case	Description	Expected Result
TC1	No Op	Input passed unchanged
TC2	Logical Left Shift	`00000001 << 4` equals `00000010`
TC3	Logical Right Shift	`80000000 >> 4` equals `08000000`
TC4a	Rotate Left (1 bit)	`00000001` rotates to `00000002`
TC4b	Rotate Left (MSB)	`80000000` rotates to `00000001`
TC4c	Rotate Left (0 bits)	Input passed unchanged
TC4d	Rotate Left (31 bits)	`00000001` rotates to `80000000`

All test cases passed successfully in simulation. The simulation log confirms zero errors.

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