Shift & Bit Manipulation

32-bit Synthesizable Barrel Shifter — L2 Upgrade

A 32-bit barrel shifter supporting logical, arithmetic, and serial shift operations with parallel load capability.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

32-bit Synthesizable Barrel Shifter — L2 Upgrade is a SystemVerilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

A fully synthesizable 32-bit barrel shifter IP core supporting logical, arithmetic, and serial shift operations. Designed for high-performance data path applications with Verilator verification.

This IP provides a robust 32-bit barrel shifter capable of parallel loading and seven distinct shift modes.

It is fully synthesizable, verified with Verilator, and includes a comprehensive testbench.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-bit Synthesizable Barrel Shifter — L2 Upgrade.
Read the SystemVerilog module in the editor. The catalog line for this block: A 32-bit barrel shifter supporting logical, arithmetic, and serial shift operations with parallel load capability.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

32-bit Data Path: Handles 32-bit wide data words.
Parallel Load: Supports direct loading of data via load_en.
Seven Shift Modes:

- Logical Shift Left (LSL) - Logical Shift Right (LSR) - Arithmetic Shift Left (ASL) - Arithmetic Shift Right (ASR) - Preserves sign bit - Serial Shift Left (SSL) - Serial Shift Right (SSR) - Parallel Load Mode

Synthesizable: Verified for synthesis with standard EDA tools.
Verified: All modes tested with Verilator.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`data_in`	Input	32	Data input for parallel load
`shift_amount`	Input	5	Shift amount (0-31)
`serial_in`	Input	1	Serial input bit
`mode`	Input	3	Operation mode selector
`load_en`	Input	1	Parallel load enable
`data_out`	Output	32	Shifted data output

Verification

The testbench (tb/tb_barrel_shifter_32bit_synthesizable_serial_in_arith.sv) verifies all seven operational modes using Verilator.

Test Case	Mode	Input	Expected Output	Result
TC1	Parallel Load	0xDEADBEEF	0xDEADBEEF	PASS
TC2	Logical Shift Left	0x00000001 (<<4)	0x00000010	PASS
TC3	Logical Shift Right	0x80000000 (>>4)	0x08000000	PASS
TC4	Arithmetic Shift Right	0x80000000 (>>>4)	0xF8000000	PASS
TC5	Serial Shift Left	0x00000000 (in=1)	0x00000001	PASS
TC6	Serial Shift Right	0x00000000 (in=1)	0x80000000	PASS

More in Shift & Bit Manipulation

All Shift & Bit Manipulation blocks