Shift & Bit Manipulation
Byte Rotate 32-bit
Combinational module that rotates a 32-bit word by 0 to 3 bytes.
About this block
Simulate it in the Verilog IDE
Byte Rotate 32-bit is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP rotates the four bytes of a 32-bit word by a specified count. It supports rotation amounts from 0 to 3 bytes. The implementation uses combinational logic for high throughput. The shift amount is controlled by a 2-bit input signal.
This module provides a simple and efficient byte rotation for 32-bit data. It is suitable for data packing and unpacking applications. The design is fully combinational and easy to integrate.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Byte Rotate 32-bit.
- Read the Verilog module in the editor. The catalog line for this block: Combinational module that rotates a 32-bit word by 0 to 3 bytes.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Rotates 32-bit data by 0, 1, 2, or 3 bytes.
- Pure combinational logic with no clock dependency.
- Supports arbitrary 32-bit input values.
- Verified with comprehensive testbench cases.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| data_in | Input | 32 | Input data word to be rotated |
| shift_bytes | Input | 2 | Number of bytes to rotate right (0-3) |
| data_out | Output | 32 | Rotated output data word |
Verification
The testbench covers all rotation counts and edge cases. All seven test cases passed successfully.
| Test Case | Input Data | Shift Bytes | Expected Output | Result |
|---|---|---|---|---|
| TC1 | 0xFDEADBEEF | 0 | 0xFDEADBEEF | PASS |
| TC2 | 0xFDEADBEEF | 1 | 0xEEFDEADB | PASS |
| TC3 | 0xFDEADBEEF | 2 | 0xDBEEFDEA | PASS |
| TC4 | 0xFDEADBEEF | 3 | 0xEADBEEFD | PASS |
| TC5 | 0x12345678 | 1 | 0x78123456 | PASS |
| TC6 | 0x00000000 | 1 | 0x00000000 | PASS |
| TC7 | 0xFFFFFFFF | 3 | 0xFFFFFFFF | PASS |
More in Shift & Bit Manipulation
- 16-Bit Bidirectional Shift Register (L/R + Load)
- 32-Bit Barrel (Nop / LSL / LSR / ROL)
- 32-Bit Funnel Shifter
- 32-bit Synthesizable Barrel Shifter — L2 Upgrade
- 8-Bit Barrel (Shift/Rotate × Left/Right) — L1 Upgrade — L2 Upgrade
- 8-Bit Bit Reversal (Endianness Independent) — L1 Upgrade
- 8-Bit Bit Reversal (Endianness Swap) — L1 Upgrade — L2 Upgrade
- 8-Bit Byte-Swap (Endianness Converter) — L1 Upgrade
- 8-Bit Parallel-to-Serial Converter
- 8-Bit Uni-Dir Shift Register (Load + SI) — L1 Upgrade — L2 Upgrade
- Arithmetic Right Shift 8-Bit — L1 Upgrade
- Bit-Field Extract 16→8
- Bitfield Pack Insert 32-bit
- Circular Shift Param 8-bit
- Funnel Shift Merge 16-bit — L2 Upgrade
- Nibble Interleave / Deinterleave 16-bit — L2 Upgrade