Shift & Bit Manipulation

8-Bit Bit Reversal (Endianness Swap) — L1 Upgrade — L2 Upgrade

8-bit bit reversal module with parallel and serial input modes and registered output.

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8-Bit Bit Reversal (Endianness Swap) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP provides a configurable 8-bit bit reversal module with support for both parallel and serial data inputs.

It is designed for high-speed digital systems requiring endianness conversion or serial-to-parallel data alignment.

The module features registered outputs for stable timing, asynchronous reset, and mode selection between immediate parallel swapping and 8-cycle serial accumulation.

Parallel Mode: Instantly reverses the bit order of data_in upon enable assertion.
Serial Mode: Accumulates 8 bits from serial_in (LSB first) over 8 clock cycles, then outputs the reversed result.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Bit Reversal (Endianness Swap) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit bit reversal module with parallel and serial input modes and registered output.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Data Width: Processes standard byte-sized data.
Dual Input Modes:

- Parallel: Immediate bit reversal with 1-cycle latency. - Serial: Shift-register accumulation over 8 cycles.

Registered Output: Ensures setup/hold time compliance in synchronous designs.
Control Signals:

- rst_n: Active-low asynchronous reset. - en: Enable signal to process data. - mode: Selects between Parallel (0) and Serial (1) operation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	System clock
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Enable signal (High = Process)
`mode`	Input	1	Mode Select (0=Parallel, 1=Serial)
`data_in`	Input	[7:0]	Parallel data input
`serial_in`	Input	1	Serial data input (LSB first)
`valid_out`	Output	1	Output valid flag
`data_out`	Output	[7:0]	Reversed/swapped data output

Architecture

The module utilizes a shift register for serial accumulation and combinational logic for parallel swapping.

Parallel Path: Uses a continuous assignment to reverse bit order. When mode is 0, the swapped data is loaded into the output register on the next clock edge.
Serial Path: When mode is 1, bits shift into a register. A 3-bit counter tracks the 8 cycles. After 8 cycles, the accumulated data is loaded into the output register, and valid_out is asserted.

Verification

The included testbench verifies parallel swapping, serial shifting, valid flag behavior, and reset conditions. All test cases passed successfully.

Test Case	Description	Result
TC1	Parallel Swap 0xAA -> 0x55	PASS
TC2	Parallel Swap 0xF0 -> 0x0F	PASS
TC3	Parallel Swap 0x00 -> 0x00	PASS
TC4	Serial Shift Data 0x55	PASS
TC5	Serial Valid Flag Early	PASS
TC6	Disable Valid	PASS
TC7	Reset Data	PASS

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