Shift & Bit Manipulation

Circular Shift Param 8-bit

Combinational module performing circular left shift on 8-bit data with variable shift amount.

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Circular Shift Param 8-bit is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a parameterized circular left shift operation on an 8-bit data bus. It uses a case-based conditional assignment to handle shift amounts from 0 to 7. The design avoids variable part-select indexing errors by explicitly defining each shift case.

This IP provides a robust and verified circular shift function for 8-bit data. It is suitable for applications requiring bit manipulation without clock synchronization.

Choose Open in IDE. RTL Studio loads the packaged workspace for Circular Shift Param 8-bit.
Read the Verilog module in the editor. The catalog line for this block: Combinational module performing circular left shift on 8-bit data with variable shift amount.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Performs circular left shifts on 8-bit input data.
Supports shift amounts from 0 to 7 via a 3-bit control signal.
Combinational logic implementation with no clock dependency.
Fully verified with 10 test cases covering all shift amounts and edge cases.

Interface

Signal	Direction	Width	Description
data_in	Input	[7:0]	Input data bus
shamt	Input	[2:0]	Shift amount (0-7)
data_out	Output	[7:0]	Output data after circular shift

Architecture

The module uses a continuous assignment with a ternary operator chain to map each shift amount to its corresponding bit concatenation. This approach ensures deterministic timing and avoids synthesis issues related to variable indexing.

Verification

The testbench applies all possible shift amounts (0-7) to two distinct data patterns (0xAA and 0x00/0xFF). It also verifies edge cases such as zero shift and full rotation.

Test Case	Input Data	Shift Amount	Expected Output	Status
TC1	8'hAA	0	8'hAA	PASS
TC2	8'hAA	1	8'h55	PASS
TC3	8'hAA	2	8'hAA	PASS
TC4	8'hAA	3	8'h55	PASS
TC5	8'hAA	4	8'hAA	PASS
TC6	8'hAA	5	8'h55	PASS
TC7	8'hAA	6	8'hAA	PASS
TC8	8'hAA	7	8'h55	PASS
TC9	8'h00	4	8'h00	PASS
TC10	8'hFF	3	8'hFF	PASS

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