Shift & Bit Manipulation

Nibble Rotate 16-Bit — L1 Upgrade

16-bit shift/rotate module supporting LSR, LSL, Nibble Rotate Right, and Arithmetic Shift Right with registered output.

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Nibble Rotate 16-Bit — L1 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) implements a 16-bit data path capable of four distinct shift and rotate operations: Logical Shift Right (LSR), Logical Shift Left (LSL), Nibble Rotate Right (NRR), and Arithmetic Shift Right (ASR). The design features a registered output to ensure stable timing and latch-free behavior, making it suitable for high-frequency L1 cache upgrades or similar low-latency data path requirements.

### Key Features

16-bit Data Width: Processes 16-bit data words.
Four Operation Modes: Configurable via a 2-bit mode input.

- 2'b00: Logical Shift Right (LSR) - Inserts 0 at MSB. - 2'b01: Logical Shift Left (LSL) - Inserts 0 at LSB. - 2'b10: Nibble Rotate Right (NRR) - Rotates 4-bit nibbles. - 2'b11: Arithmetic Shift Right (ASR) - Replicates MSB (sign bit).

Registered Output: data_out is registered to provide stable timing.
Handshake Interface: Uses valid to trigger operations and ready to indicate availability.
Synchronous Load: load signal allows direct loading of data_in into the internal register.

Choose Open in IDE. RTL Studio loads the packaged workspace for Nibble Rotate 16-Bit — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 16-bit shift/rotate module supporting LSR, LSL, Nibble Rotate Right, and Arithmetic Shift Right with registered output.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
load	Input	1	Load data_in into register
valid	Input	1	Trigger shift/rotate operation
mode	Input	2	Operation mode selector
data_in	Input	16	Input data word
data_out	Output	16	Output data word
ready	Output	1	Handshake ready signal (asserts high when valid is high)

Architecture

The design consists of a single synchronous process that updates internal state on the positive edge of the clock.

Registers: Two 16-bit registers are used:

- data_reg: Holds the current value being shifted/rotated. - data_out_reg: Holds the registered output value.

Priority: The load signal takes priority over valid for data entry.
Operation: When valid is high (and load is low), the mode signal determines the transformation applied to data_reg.
Output: The external data_out is driven by data_out_reg. Note that data_out reflects the result of the previous cycle's operation due to the registered output stage.

Verification

The included testbench verifies all functional modes, including reset and load functionality.

### Test Cases

Test Case	Description	Result
TC1	Load and Readback	PASS
TC2	Logical Shift Right (LSR)	PASS
TC3	Logical Shift Left (LSL)	PASS
TC4	Nibble Rotate Right (NRR)	PASS
TC5	Arithmetic Shift Right (ASR)	PASS
TC6	Ready Signal Check	PASS

### Simulation Log

Upon running the simulation, the following output indicates success:

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