Shift & Bit Manipulation

Rotate Left/Right 8-Bit — L1 Upgrade — L2 Upgrade

8-bit serial-in shift register with parallel load, supporting left/right shift modes and serial data injection.

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Rotate Left/Right 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit serial-in shift register with parallel load capability.

It supports configurable shifting directions (left or right) controlled by a mode signal, making it suitable for arithmetic operations, serial data processing, and FIFO-like buffer implementations.

The design includes synchronous reset and enable controls for flexible integration into larger digital systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for Rotate Left/Right 8-Bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit serial-in shift register with parallel load, supporting left/right shift modes and serial data injection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Width: Processes 8-bit data words.
Parallel Load: Loads 8-bit data from data_in when en is low.
Serial Shift: Shifts data serially when en is high.
Bidirectional Shifting:

- Left Shift: Inserts serial_in at the Least Significant Bit (LSB). - Right Shift: Inserts serial_in at the Most Significant Bit (MSB).

Synchronous Reset: Resets the register to zero on the active-low rst_n signal.
Fully Verified: Comprehensive testbench coverage for all operational modes.

Architecture

The core logic is implemented within a single synchronous process triggered by the clock (clk) and reset (rst_n).

Reset: When rst_n is low, the internal register shift_reg is cleared to 8'b0.
Enable Logic:

- If en is low: The register loads the parallel input data_in. - If en is high: The register performs a shift operation based on the mode signal. - mode == 0 (Left Shift): shift_reg <= {shift_reg[6:0], serial_in} - mode == 1 (Right Shift): shift_reg <= {serial_in, shift_reg[7:1]}

### Block Diagram

Interface

Signal	Direction	Width	Description
clk	Input	1	Clock signal
rst_n	Input	1	Active-low synchronous reset
en	Input	1	Enable: 0=Load, 1=Shift
mode	Input	1	Direction: 0=Left, 1=Right
serial_in	Input	1	Serial data input for shift operation
data_in	Input	8	Parallel data input for load operation
data_out	Output	8	Current state of the shift register

Verification

The provided testbench (tb_rotate_left_right_arithmetic_mode_8bit_serial_in_arith.v) verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Parallel Load 0xAA	`data_out` == 0xAA
TC2	Shift Left (0x01 -> 0x02 -> 0x04)	Correct left shift
TC3	Shift Right (0x80 -> 0x40 -> 0x20)	Correct right shift
TC4	Serial In Left (1) into 0x00	`data_out` == 0x01
TC5	Serial In Right (1) into 0x00	`data_out` == 0x80
TC6	Reset to 0x00	`data_out` == 0x00

Run the simulation to view waveforms in sim/dump.vcd and verify the log output indicates PASS for all test cases.

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