Shift & Bit Manipulation

Universal Shift Register 8-Bit — L2 Upgrade

An 8-bit universal shift register supporting parallel load, bidirectional serial shifting, and valid status output.

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Universal Shift Register 8-Bit — L2 Upgrade is a Verilog reference block in the Shift & Bit Manipulation catalog. Shifters, rotators, bit masks, and bitwise manipulation blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a robust 8-bit universal shift register with parallel load capability. It supports bidirectional shifting (left and right) via a single direction control signal. Serial data can be shifted in from either the MSB or LSB depending on the direction. Parallel data loading is supported for immediate state initialization. A valid_out flag indicates when the register holds valid parallel-loaded or shifted data. The design is synchronous with an active-low asynchronous reset.

This IP is fully verified using Icarus Verilog and is ready for integration into larger digital systems for data serialization and deserialization tasks.

Choose Open in IDE. RTL Studio loads the packaged workspace for Universal Shift Register 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit universal shift register supporting parallel load, bidirectional serial shifting, and valid status output.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Width: Configurable for standard byte-sized data operations.
Bidirectional Shifting: Supports both Left and Right shifts controlled by a single signal.
Parallel Load: Immediate state initialization via parallel input.
Validity Flag: valid_out indicates when data is stable and valid.
Asynchronous Reset: Active-low reset for quick initialization.
Synthesizable: Standard Verilog-2001 compliant code.

Architecture

The core component is an 8-bit flip-flop array managed by a multiplexer structure. The multiplexer selects between parallel input, left-shifted data, or right-shifted data. The shift direction is controlled by the shift_dir input signal. Serial input enters at the appropriate end of the register based on the direction. Serial output is tapped from the opposite end of the shift direction.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous operations.
`rst_n`	Input	1	Active-low asynchronous reset.
`load`	Input	1	Parallel load enable. High loads `parallel_in`.
`shift_en`	Input	1	Shift enable. High allows shifting on clock edge.
`shift_dir`	Input	1	Shift direction. 0=Right, 1=Left.
`serial_in`	Input	1	Serial data input. Enters MSB (Right) or LSB (Left).
`parallel_in`	Input	8	Parallel data input for load operation.
`data_out`	Output	8	Current content of the shift register.
`serial_out`	Output	1	Serial data output. Taps MSB (Right) or LSB (Left).
`valid_out`	Output	1	Valid flag. High during load, stays high during shift, low otherwise.

Verification

The testbench covers five primary scenarios to ensure correct functionality. All tests passed successfully in the Icarus Verilog simulation environment.

Test Case	Description	Expected Result	Status
TC1	Parallel Load with 0xAA	`data_out` = 0xAA, `valid_out` = 1	PASS
TC2	Shift Right with Serial In 0	Register clears to 0x00 after 8 shifts	PASS
TC3	Shift Right with Serial In 1	Register fills to 0xFF after 8 shifts	PASS
TC4	Shift Left with Serial In 0	Register clears to 0x00 after 8 shifts	PASS
TC5	Shift Left with Serial In 1	Register fills to 0xFF after 8 shifts	PASS

Constraints

Timing: No specific timing constraints are defined; ensure setup/hold times are met by your target technology.
Synthesis: Compatible with standard CMOS processes. No special primitives used.

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