Clock Generators

Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade

Latch-free, fully synthesizable clock divider with burst, freeze, and clear capabilities. Uses m, n, and div inputs in the comparison logic to ensure no unused ports.

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About this block

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Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a latch-free, fully synthesizable clock divider with support for dynamic divider selection, burst enable, freeze, and clear capabilities. It is designed for applications requiring precise timing control, frequency synthesis, and clock gating.

### Key Features

Dynamic Divider Selection: Supports three 8-bit inputs (div, n, m) with a priority chain: div > n > m.
Control Signals:

- enable: Synchronous pause/resume of counting. - freeze: Holds the current output state without resetting the counter. - clear: Synchronous reset of counter and output. - rst_n: Asynchronous active-low reset.

Synthesis Friendly: All input ports are functionally utilized to prevent unused port warnings. No latches are inferred.
Verilog-2001 Compatible: Fully synthesizable code.

Choose Open in IDE. RTL Studio loads the packaged workspace for Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Latch-free, fully synthesizable clock divider with burst, freeze, and clear capabilities. Uses m, n, and div inputs in the comparison logic to ensure no unused ports.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`enable`	Input	1	Synchronous enable to start/stop counting
`freeze`	Input	1	Synchronous freeze to hold output state
`clear`	Input	1	Synchronous clear to reset counter and output
`m`	Input	8	Fallback divider value (used if `div` and `n` are 0)
`n`	Input	8	Secondary divider value (used if `div` is 0)
`div`	Input	8	Primary divider value
`out`	Output	1	Toggled output signal

Verification

The provided testbench (tb_burst_enable_freeze_clear_enable_div_used_mn.v) verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset and Clear functionality	Output is low, counter resets
TC2	Freeze and Resume	Output holds state while frozen, resumes after
TC3	M and N Fallback Logic	Divider uses `n` when `div` is 0, `m` as final fallback
TC4	Enable Low (Disable)	Output holds state when enable is low
TC5	M Input Presence	M is connected and does not cause synthesis errors

### Running Simulation

Expected log output:

TC1 PASS Clear
TC2 PASS Freeze
TC2 PASS Freeze/Resume structure
TC3 PASS M/N Fallback
TC4 PASS Enable Low
TC5 PASS M Input Presence
Simulation ends with INFO: PASS

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