Clock Generators

Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade

Configurable clock-enable stretcher with busy-handshaking support and m/n ratio control.

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About this block

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Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a configurable clock-enable (CE) stretcher with busy-handshaking support. It generates a stretched enable pulse based on an m/n ratio. The module pauses counting when an external busy_in signal is asserted and resumes counting once busy_in de-asserts. The output ce_out is asserted when the internal counter equals m and the internal busy state is active.

This module is suitable for scenarios where downstream logic requires a guaranteed minimum pulse width or where the clock enable must be gated by a busy signal without losing the cycle count.

Choose Open in IDE. RTL Studio loads the packaged workspace for Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Configurable clock-enable stretcher with busy-handshaking support and m/n ratio control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

Signal	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Active-low reset
ce_in	input	1	Clock-enable trigger. Asserting this starts a new cycle.
busy_in	input	1	External busy inhibit. Pauses counting if asserted during a cycle.
m	input	8	CE assertion point (0 to n-1). `ce_out` asserts when `cnt == m`.
n	input	8	Total cycle length (1 to 255).
ce_out	output	1	Stretched clock enable. Asserted for one cycle when `cnt == m` and `busy_int` is high.
busy_out	output	1	Busy status flag. Asserted when a cycle is in progress.

Architecture

The core logic involves an 8-bit counter (cnt) and an internal busy state register (busy_int).

Cycle Start: When ce_in is asserted and the module is idle (busy_int == 0), busy_int becomes 1, and cnt resets to 1.
Counting Logic: The counter increments on every clock cycle while busy_int is 1 and busy_in is 0.
Busy Inhibition: If busy_in is asserted while busy_int is 1, the counter holds its value until busy_in de-asserts. The cycle continues from where it paused.
Cycle Completion: Once the counter reaches n-1, it resets to 0, and busy_int clears to 0, ending the cycle.
Output Generation: ce_out is asserted for one clock cycle when cnt == m AND busy_int == 1.

Constraints

n must be greater than 0 (1 to 255).
m must be less than n (0 to n-1).
ce_in should be synchronized to clk to avoid metastability.
busy_in should be synchronized to clk to avoid metastability.
If m >= n, the behavior is undefined or ce_out may never assert.

Verification

The IP has been verified using a comprehensive testbench. The following test cases confirm correct behavior:

Test Case	Description	Result
TC1	Basic Reset Check	PASS
TC2	Single Pulse Generation	PASS
TC3	Busy Inhibition	PASS
TC4	Divider Ratio Check	PASS
TC5	Verify ce_out Value	PASS

To run the simulation, execute the provided script in the sim/ directory. The simulation log should conclude with INFO: PASS.

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