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Clock Generators

Dual-Edge DDR Sampler — L2 Upgrade

Dual-edge DDR sampler with configurable clock division and enable control.

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About this block

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Dual-Edge DDR Sampler — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a Dual-Edge DDR Sampler capable of sampling input data on both the positive and negative edges of a clock signal. It features configurable clock division and enable control, making it suitable for high-throughput data interfaces where bandwidth efficiency is critical.

The design ensures synchronous operation with an active-low reset and provides a clean, alternating output stream based on the configured division ratio.

This IP provides a robust, configurable solution for dual-edge data sampling.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Dual-Edge DDR Sampler — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Dual-edge DDR sampler with configurable clock division and enable control.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Dual-Edge Sampling: Captures data on both posedge and negedge of the clock.
  • Configurable Division: Supports clock division ratios via the div input (divides by div + 1).
  • Enable Control: Synchronous enable (en) allows dynamic start/stop of sampling.
  • Synchronous Reset: Active-low reset (rst_n) clears all internal states.
  • 8-bit Data Path: Handles 8-bit parallel data input and output.

Architecture

The module is composed of three main stages:

  1. Divider Generator: Counts clock cycles and asserts a pulse (div_en) every div + 1 cycles.
  2. Dual-Edge Sampler: Two registers capture data_in on the positive and negative edges respectively when div_en is active.
  3. Output Mux: Alternates between the positive-edge sample (d_reg) and negative-edge sample (q_reg) based on the LSB of the divider counter.

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