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Clock Generators

Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade

Duty-correct divide-by-N using M/N ratio with enable and registered output.

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About this block

Simulate it in the Verilog IDE

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Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a configurable frequency divider with precise duty cycle control. It uses two independent counters to define the division ratio (M) and the high-time duration (N), ensuring a duty cycle of N/M.

Key features include:

  • Configurable Division Ratio: Supports division ratios from 1 to 15.
  • Precise Duty Cycle: Adjustable high-time from 1 to M cycles.
  • Registered Output: Glitch-free output staging.
  • Dynamic Control: Supports dynamic enable/disable.

The core logic utilizes two independent 4-bit counters:

  • M Counter: Defines the total period length (1-15 cycles).
  • N Counter: Defines the high-time duration (1-M cycles).
  • m (Period Divisor): Range 1-15
  • n (High-Time Divisor): Range 1 to m
  • Critical: n must always be less than or equal to m.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Duty-correct divide-by-N using M/N ratio with enable and registered output.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

PortDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
enInput1Enable signal (active high)
mInput[3:0]Period divisor (M). Range: 1-15
nInput[3:0]High-time divisor (N). Range: 1-M
clk_outOutput1Divided clock output
busyOutput1Active high when en is asserted

Architecture

The internal architecture consists of:

  1. Counter Logic: Two synchronous counters (cnt_m and cnt_n) that increment on each clock cycle when enabled.
  2. Duty Cycle Logic: Combinational logic comparing cnt_m with n to determine the output state.
  3. Output Registration: Registered output (out_reg) to ensure clean clock transitions.

Verification

The provided testbench (tb_duty_correct_div2_enable_registered_enable_div_used_mn.v) covers:

  • Reset Behavior: Verifies clk_out and busy are low after reset.
  • Enable/Disable: Checks state transitions when enabling and disabling the divider.
  • Duty Cycle Accuracy: Validates output waveforms for various M/N combinations.

### Running Simulation

To run the simulation:

  1. Open your preferred Verilog simulator (e.g., ModelSim, VCS, Xcelium).
  2. Compile the RTL and testbench files.
  3. Run the simulation.

### Expected Results

  • TC1 PASS: Reset check
  • TC2 PASS: Enable M=4 N=2
  • TC3 PASS: Disable check
  • TC4 PASS: Enable M=8 N=2
  • TC5 PASS: Enable M=2 N=2
  • INFO: PASS

More in Clock Generators

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