Clock Generators

Fractional Clock Enable M/N — L2 Upgrade

Fractional Clock Enable M/N with Used-MN Indicator using Bresenham accumulator.

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About this block

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Fractional Clock Enable M/N — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a fractional clock enable generator using an M/N ratio.

It utilizes a Bresenham accumulator algorithm to distribute pulses evenly, ensuring minimal jitter in the output enable signal.

The module supports configurable M and N parameters for precise frequency scaling and is suitable for power management and clock domain crossing applications.

Choose Open in IDE. RTL Studio loads the packaged workspace for Fractional Clock Enable M/N — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Fractional Clock Enable M/N with Used-MN Indicator using Bresenham accumulator.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Fractional Division: Divides input clock enable (ce_in) to ce_out based on an M/N ratio.
Bresenham Algorithm: Uses accumulation for uniform pulse distribution.
Configurable: M and N values are configurable via 8-bit inputs (0-255). Note: N should typically be > 0.
Status Indicator: used_mn flag indicates active division state (m > 0).
Synchronous Reset: Clean initialization behavior with active-low reset.

Ports

Port	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Active-low synchronous reset
ce_in	input	1	Input clock enable signal
m	input	[7:0]	Numerator of the fractional ratio
n	input	[7:0]	Denominator of the fractional ratio
ce_out	output	1	Output clock enable signal
used_mn	output	1	Active-high indicator when m > 0

Verification

The testbench verifies reset behavior, basic 50% duty cycle, m=0 case, m > n wrapping, and ce_in gating.

### Expected Results

After Run Simulation, the Log panel should show:

TC1 PASS ce_out is 0 during reset
TC1 PASS used_mn is 0 during reset
TC2 PASS ce_out high count 5
TC2 PASS used_mn is high when m > 0
TC3 PASS ce_out is 0 when m=0
TC3 PASS used_mn is 0 when m=0
TC4 PASS ce_out high count 6
TC5 PASS ce_out is 0 when ce_in=0

### Test Cases

Test Case	Description	Result
TC1	Reset behavior	PASS
TC2	Basic 50% duty cycle (m=5, n=10)	PASS
TC3	m=0 case (no output)	PASS
TC4	m > n case (wrapping)	PASS
TC5	ce_in gating	PASS

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