Clock Generators

4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade

Glitch-free 4-phase clock-enable sequencer with configurable M/N division counters.

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About this block

Simulate it in the Verilog IDE

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4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a glitch-free 4-phase clock-enable sequencer with configurable M/N division ratios.

It generates a clean enable pulse (ce_out) and a divided clock pulse (div_out).

The sequencer ensures glitch-free transitions by synchronizing phase changes to the M-counter match signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Glitch-free 4-phase clock-enable sequencer with configurable M/N division counters.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Glitch-Free Operation: Outputs are latched on M-counter match events to prevent transition glitches.
Configurable Division: Supports 8-bit M and N configuration for flexible division ratios.
4-Phase Sequence: Generates a 4-phase sequence (00, 01, 10, 11) driven by the M-counter.
Divided Pulse: Outputs a single-cycle pulse on div_out every N+1 cycles.
Asynchronous Reset: Active-low reset (rst_n) initializes all counters and phases.

Ports

Port	Direction	Width	Description
`clk`	Input	1	System clock
`rst_n`	Input	1	Asynchronous active-low reset
`ce_in`	Input	1	Clock enable input (gates counters)
`m`	Input	[7:0]	M counter modulus (divides by M+1)
`n`	Input	[7:0]	N counter modulus (divides by N+1)
`ce_out`	Output	1	Glitch-free 4-phase enable output
`div_out`	Output	1	Divided clock pulse output

Architecture

The design consists of two independent counters and a state sequencer:

M-Counter: Divides the input enable rate to drive the phase sequencer. It resets when it matches the m input.
N-Counter: Divides the input clock to generate the div_out pulse. It resets when it matches the n input.
Phase Sequencer: Updates its state only when the M-counter matches the target value (m_match). This synchronization prevents glitches during phase transitions.

Verification

The testbench verifies reset behavior, division ratios, and enable gating. All tests passed in the Icarus Verilog simulation.

Test Case	Description	Result
TC1	Reset Behavior	PASS
TC2	M=1, N=1 Division	PASS
TC3	M=3, N=3 Division	PASS
TC4	ce_in Low Gating	PASS
TC5	M=0, N=0 Max Freq	PASS

Expected Log Output:

TC1 PASS
TC2 PASS div_out is active
TC3 PASS div_out is active
TC4 PASS
TC5 PASS div_out is active
Simulation ends with INFO: PASS.

Constraints

Clock Domain: Synchronous to clk.
Reset: Asynchronous active-low reset.
Frequency: No specific maximum frequency constraint defined; depends on target technology.
Power: Low power mode enabled via ce_in gating.

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