Clock Generators
16-Bit DDS Phase Accumulator — L2 Upgrade
16-bit DDS phase accumulator with dual phase output, freeze, and stretch control.
About this block
Simulate it in the Verilog IDE
16-Bit DDS Phase Accumulator — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP core implements a 16-bit Direct Digital Synthesis (DDS) phase accumulator with dual-phase output capabilities.
It is designed for high-performance FPGA and ASIC implementations, supporting advanced waveform synthesis through precise control of phase accumulation timing.
The design includes features such as Clock Enable, Freeze, and Stretch modes, and has been fully verified using Icarus Verilog.
phase_out: The current accumulated phase value.phase_out_dual: The phase value plus the current offset, enabling phase-shifted waveform generation.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit DDS Phase Accumulator — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: 16-bit DDS phase accumulator with dual phase output, freeze, and stretch control.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 16-Bit Precision: Full 16-bit phase resolution for accurate frequency generation.
- Dual-Phase Output: Simultaneous generation of main phase and phase-shifted output.
- Flexible Control Modes:
- Clock Enable (ce): Gates the accumulation logic. Accumulation only occurs when ce is high. - Freeze (freeze): Holds the current phase value constant, stopping accumulation. - Stretch (stretch): Delays the accumulation by one clock cycle, effectively halving the update rate when asserted.
- Reset: Active-low asynchronous reset (
rst_n) initializes both phase registers to zero.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Clock input |
rst_n | Input | 1 | Active-low reset |
ce | Input | 1 | Clock enable (accumulation gated when low) |
freeze | Input | 1 | Freeze phase output (holds value when high) |
stretch | Input | 1 | Stretch accumulation cycle (delays update by 1 cycle) |
phase_offset | Input | [15:0] | Phase increment value |
phase_out | Output | [15:0] | Current phase accumulator value |
phase_out_dual | Output | [15:0] | Dual phase output (phase + offset) |
Verification
The testbench covers the following scenarios:
- TC1: Reset to zero
- TC2: Normal accumulation
- TC3: Freeze mode
- TC4: Dual phase output
- TC5: Stretch cycle
- TC6: Clock enable low
Expected Simulation Output:
More in Clock Generators
- 1-Cycle Data Delay
- 2:1 Clock Divider (Toggle Flip-Flop)
- 4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade
- Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade
- CE Pulse Every N Cycles
- Clock Enable with Soft-Reset Stretch — L2 Upgrade
- Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade
- Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade
- Divide-by-3 Clock (50% Duty)
- Dual-Edge DDR Sampler — L2 Upgrade
- Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade
- Fractional Clock Divider with Jitter Control
- Fractional Clock Enable M/N — L2 Upgrade
- Glitch-Free Clock Select 2 — L2 Upgrade
- Integer Clock Divider
- Lost-Clock Detector — L2 Upgrade